m36l0r7060t1 STMicroelectronics, m36l0r7060t1 Datasheet - Page 10

• Manufacturer Part Number: m36l0r7060t1
• Description: 128 Mbit Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit Burst Psram, 1.8 V Supply, Multichip Package
• Manufacturer: STMicroelectronics

Signal descriptions
2.5
2.6
2.7
2.8
2.9
2.10
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Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the
WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details of how it behaves, please refer to the M69KB096AM datasheet for the PSRAM
and to the M58LR128HTB datasheet for the Flash memory.
Flash Chip Enable (E
The Flash Chip Enable input activates the control logic, input buffers, decoders and sense
amplifiers of the Flash memory component. When Chip Enable is Low, V
High, V
deselected, the outputs are high impedance and the power consumption is reduced to the
standby level.
Flash Output Enable (G
The Output Enable pin controls the data outputs during Flash memory Bus Read
operations.
Flash Write Enable (W
The Write Enable controls the Bus Write operation of the Flash memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
Flash Write Protect (WP
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V
Down blocks cannot be changed. When Write Protect is at High, V
and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the
M30L0R7000T1/B1 datasheet).
Flash Reset (RP
The Reset input provides a hardware reset of the Flash memory. When Reset is at V
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
value of I
reset. When Reset is at V
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied
to V
RPH
IH
(refer to the M58LR128HTB datasheet).
DD2
, the device is in active mode. When Chip Enable is at V
. After Reset all blocks are in the Locked state and the Configuration Register is
IL
F
, Lock-Down is enabled and the protection status of the Locked-
)
IH
, the device is in normal operation. Exiting Reset mode the
F
)
F
)
F
F
)
)
DD2
. Refer to the M58LR128HTB datasheet, for the
M36L0R7060T1, M36L0R7060B1
IH
IH
, Lock-Down is disabled
the Flash memory is
IL
, and Reset is
IL
, the