m36l0r8060t0 STMicroelectronics, m36l0r8060t0 Datasheet - Page 6

• Manufacturer Part Number: m36l0r8060t0
• Description: 256 Mbit Multiple Bank, Multi-level, Burst Flash Memory 64 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
• Manufacturer: STMicroelectronics

M36L0R8060T0, M36L0R8060B0
SIGNAL DESCRIPTIONS
See
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A23). Addresses
are common inputs for the Flash memory and
PSRAM components. The other lines (A23-A22)
are inputs for the Flash memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory internal state machine or they select the
cells to access in the PSRAM.
The Flash memory is accessed through the Chip
Enable signal (
signal (W
the Chip Enable signal (E
signal (W
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Bus Write op-
eration.
For the PSRAM component, the upper Byte Data
Inputs/Outputs (DQ8-DQ15) carry the data to or
from the upper part of the selected address when
Upper Byte Enable (UB
Byte Data Inputs/Outputs (DQ0-DQ7) carry the
data to or from the lower part of the selected ad-
dress when Lower Byte Enable (LB
Low. When both UB
Data Inputs/ Outputs are high impedance.
Latch Enable (L). The Latch Enable pin is com-
mon to the Flash memory and PSRAM compo-
nents.
For details of how the Latch Enable signal be-
haves, please refer to the datasheets of the re-
spective memory components: M69KR096A for
the PSRAM and M30L0R8000T/B0 for the Flash
memory.
Clock (K). The Clock input pin is common to the
Flash memory and PSRAM components.
For details of how the Clock signal behaves,
please refer to the datasheets of the respective
memory
PSRAM and M30L0R8000T/B0 for the Flash
memory.
Wait (WAIT). WAIT is an output pin common to
the Flash memory and PSRAM components. How-
ever the WAIT signal does not behave in the same
way for the PSRAM and the Flash memory.
For details of how it behaves, please refer to the
M69KR096A datasheet for the PSRAM and to the
M30L0R8000T/B0 datasheet for the Flash memo-
ry.
6/18
Figure 2., Logic Diagram
F
P
), while the PSRAM is accessed through
).
components:
E
F
) and through the Write Enable
P
and LB
P
) is driven Low. The lower
P
M69KR096A
) and the Write Enable
and
P
are disabled, the
Table 1., Signal
P
) is driven
for
A0-A21
the
Flash Chip Enable (E
input activates the control logic, input buffers, de-
coders and sense amplifiers of the Flash memory
component. When Chip Enable is Low, V
Reset is High, V
When Chip Enable is at V
deselected, the outputs are high impedance and
the power consumption is reduced to the standby
level.
Flash Output Enable (G
pin controls the data outputs during Flash memory
Bus Read operations.
Flash Write Enable (
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
input that gives an additional hardware protection
for each block. When Write Protect is Low, V
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, V
disabled and the Locked-Down blocks can be
locked or unlocked. (See the Lock Status Table in
the M30L0R8000T0/B0 datasheet).
Flash Reset (RP
hardware reset of the Flash memory. When Reset
is at V
are high impedance and the current consumption
is reduced to the Reset Supply Current I
to
Currents, for the value of I
blocks are in the Locked state and the Configura-
tion Register is reset. When Reset is at V
device is in normal operation. Exiting Reset mode
the device enters Asynchronous Read mode, but
a negative transition of Chip Enable or Latch En-
able is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
(refer to
tics -
PSRAM Chip Enable input (E
able input activates the PSRAM when driven Low
(asserted). When deasserted (V
disabled, and goes automatically in low-power
Standby mode or Deep Power-down mode.
PSRAM Write Enable (W
controls the Bus Write operation of the PSRAM.
When asserted (V
and Write operations can be performed either to
the configuration registers or to the memory array.
PSRAM Output Enable (G
G
P
Table 6., Flash Memory DC Characteristics -
, provides a high speed tri-state control, allow-
Voltages).
IL
, the memory is in Reset mode: the outputs
Table 7., Flash Memory DC Characteris-
IH
F
). The Reset input provides a
IL
, the device is in active mode.
), the device is in Write mode
W
F
F
). The Flash Chip Enable
). The
F
F
P
). The Output Enable
IH
). Write Protect is an
). Write Enable, W
P
). Output
the Flash memory is
DD2
P
). The Chip En-
. After Reset all
IH
IH
Write
), the device is
, Lock-Down is
DD2
Enable,
Enable
IL
. Refer
IH
, and
, the
RPH
IL
P
,
,