saa4996h NXP Semiconductors, saa4996h Datasheet - Page 33

• Manufacturer Part Number: saa4996h
• Description: Motion Adaptive Colour Plus And Control Ic Macpacic For Palplus
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.15
The control part (see Fig.2) generates all necessary
internal control signals for the MACPACIC, the external
control signals for the field memories FM1 to FM4 and the
control signals for the VERIC. All of these signals are
derived from the mode bits transmitted via the SNERT
interface or from the reference input pins.
7.15.1
The horizontal reference signal is the rising edge of the
CLAMP input pulse generated by the 100 Hz memory
controller (see Fig.30). The rising edge of WE_FRONT
defines the first active horizontal sample of the incoming
data Y_FRONT. The vertical reference signal is the rising
edge of VA_FRONT (see Fig.32), derived from the
synchronisation IC (e.g. TDA9144).
For PALplus input signals line 24 is the first processed line
related to VA_FRONT. When MACP or standard input
signals are used, line 21 is the first processed line related
to VA_FRONT.
7.15.2
The acquisition line counter (ACQ) is preset with the
delayed rising edge of VA_FRONT (see Fig.2). With the
‘VA_FRONT Delay’ circuit it is possible to shift the rising
edge of VA_FRONT in multiples of CLK_16 clock periods.
This feature is necessary for unambiguous odd/even field
detection. The delay can be set via the SNERT interface.
The ACQ line counter is preset with logic 1 at the
beginning of the odd and even fields. The counter is
enabled with the rising edge of the clamp signal.
The display line counter (DSP) is used in the event of a
stand-alone MACPACIC (IVericN = 1) and is also preset
with the delayed rising edge of VA_FRONT. If VERIC is
available the field length measurement is active.
The display line counter is preset at the beginning of a
displayed odd and even field with the rising edge of VA_AI
set to logic 1.
The pixel counter 1 is preset with the rising edge of the
CLAMP pulse. The counter is clocked with the 16 MHz
clock signal CLK_16I.
1996 Oct 28
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
Control
I
F
NPUT REFERENCE SIGNALS
UNCTIONAL DESCRIPTION
33
The rising edge of WE_FRONT marks the horizontal
location of the first active input data of MACPACIC.
The signal WE_MA defines the horizontal and vertical
active area in which the first field memory (FM5) of the
succeeding 100 Hz feature box stores incoming data.
The signal WE_MA is generated by comparing (via the
SNERT interface) the transmitted start and stop values
with the values of the display line counter and the pixel
counter 1.
The pixel counter 2 is preset with the rising edge of
WE_FRONT in such a way that the counter has the value
‘1’ when the first active input data pixel is valid at the
Y, UV_ADC input of MACPACIC. This counter is a 10-bit
modulo 1024 counter clocked with CLK_16I.
7.15.2.1
The output of pixel counter 2 is used to generate the
horizontal read and write enable signals for FM1 and FM4
and the write enable signals for the field memories FM2
and FM3. The read cycle for FM2 and FM3 is controlled by
the VERIC.
The horizontal read and write signals are different for the
full PALplus module, for stand-alone MACPACIC and for
the odd and even fields. Therefore, the signals IVericN and
EVEN_FIELD are also input to the pixel decoder.
The output of the acquisition line counter is used to
generate the vertical part of the read and write enable
signals for FM1 and FM4 and the vertical part of the write
enable signals for the field memories FM2 and FM3.
The vertical read cycle for FM2 and FM3 is controlled by
the VERIC.
The horizontal and vertical component of the read and
write enable signals are different for the full PALplus
module and for the stand-alone MACPACIC. The line
values for the memory controlling are shown in Tables 6,
7 and 8.
Memory control
Preliminary specification
SAA4996H