saa4996h NXP Semiconductors, saa4996h Datasheet - Page 35

• Manufacturer Part Number: saa4996h
• Description: Motion Adaptive Colour Plus And Control Ic Macpacic For Palplus
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 6 Pixel values for horizontal memory control
Table 7 Line values for vertical memory control, PALplus signals
Table 8 Line values for vertical memory control, MACP and standard signals
The horizontal and vertical memory control signals are
combined in the H/V logic to generate the memory read
and write signals.
In all modes, except the MultiPIP mode, the signal
VA_RES is used as a reset signal for the field memories
FM1 to FM4 (RSTW_FM23 and RST_FM14). If the
MultiPIP mode is selected, the signal VA_AI is an input
signal generated by an external memory controller. In this
event the signal VA_AI_DIFF is used as RSTW_FM23.
The signal WE_FM2 is set to logic 1 and all other read and
write enable signals are set to logic 0. If the stand-alone
MACPACIC and MultiPIP mode is selected, all memory
control signals are set to logic 0.
The output pins 46 to 48 have different output signals
depending on the environment in which MACPACIC is
used. If it is part of a full PALplus module these pins deliver
bits of chrominance data, in the stand-alone MACPACIC
mode they output memory control signals
(see Chapter “Pinning”). Selection of either mode is
performed by the control signal IVericN.
1996 Oct 28
EVEN_FIELD
EVEN_FIELD
EVEN_FIELD
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
0
0
1
1
0
0
1
1
0
0
1
1
IVericN
IVericN
IVericN
0
1
0
1
0
1
0
1
0
1
0
1
H_WE_FM1
V_WE_FM1
V_WE_FM1
26 to 865
21 to 311
21 to 311
22 to 312
21 to 311
21 to 311
22 to 312
0 to 839
2 to 841
V_RE_FM1
H_RE_FM1
V_RE_FM1
20 to 310
20 to 310
24 to 863
21 to 311
20 to 310
20 to 310
21 to 311
0 to 839
0 to 839
35
V_WE_FM2
H_WE_FM2
V_WE_FM2
7.15.2.2
The signal HREF_MA is generated by delaying the
CLAMP input signal two clocks CLK_16. The HREF_MA
signal is used in the VERIC as a clock pulse for the internal
line counter. The timing is illustrated in Fig.34.
7.15.2.3
In the VERIC control decoder of MACPACIC the output
signals FILM and INTPOL are generated as shown in
Table 9.
167 to 274
27 to 866
21 to 166
24 to 59
The output signal HREF_MA
VERIC control output signals
V_WE_FM3
H_WE_FM3
V_WE_FM3
275 to 310
167 to 311
60 to 166
27 to 866
H_WE_FM4
V_RE_FM4
V_RE_FM4
21 to 311
21 to 311
21 to 311
21 to 311
9 to 848
9 to 848
Preliminary specification
SAA4996H
V_WE_FM4
V_WE_FM4
H_RE_FM4
21 to 311
21 to 311
21 to 311
21 to 311
0 to 839
0 to 839