saa4996h NXP Semiconductors, saa4996h Datasheet - Page 36

• Manufacturer Part Number: saa4996h
• Description: Motion Adaptive Colour Plus And Control Ic Macpacic For Palplus
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 9 Generation of the signals FILM and INTPOL
7.15.2.4
On the full PALplus module the field length is measured in
the MACPACIC.
The ACQ line counter counts the lines between two
succeeding vertical pulses. The one-line-long vertical
output signal VA_AI has a delay of 1.5 fields with respect
to the delayed VA_FRONT input signal and has the same
phase relationship to the CLAMP input signal for various
video input signals (VCR, NTSC).
For the stand-alone MACPACIC the 2.5 H signal
VA_FR_DEL is selected by the control signal IVericN as
the vertical reference output signal VA_AI.
7.15.2.5
To detect the current odd or even field, the location of the
delayed VA_FRONT (VA_RES) input signal inside a line
has to be located.
For a PALplus video input signal the output signal
EVEN_FIELD is generated by enabling a register with the
VA_RES signal, which has the MSB of the pixel counter 2
at the D input.
In the bypass or MultiPIP mode the toggle function of the
register is active.
1996 Oct 28
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
22Valid
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Field length measurement
Field detection
FilmOn
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Mpip
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
HlpM0
36
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
The odd/even field detection can be inverted by the
SNERT control bit InvO/E.
It is also possible to define the EVEN_FIELD signal by
software via a SNERT transmission.
7.15.2.6
The signals VA_FRONT and VA_AI have bidirectional
functions. In all modes, except the MultiPIP mode, the pin
VA_FRONT is an input pin and the pin VA_AI is an output
pin. If the MultiPIP mode is selected the pin VA_AI is an
input pin and the signal is connected to the VA_FRONT pin
which now becomes an output pin (see Fig.2 and Fig.35).
7.15.3
In the SNERT interface the external signals SNERT_CL
and SNERT_DA are processed to address and data.
A synchronisation to the bus performed with the reset
signal SNERT_RST. The transmitted data is valid with the
next rising edge of SNERT_RST.
The block diagram and the data, clock and reset timing of
the SNERT interface are shown in Fig.3 and Fig.36.
SNERT
AN95XXX)
Pins VA_FRONT and VA_AI
HlpM1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
INTERFACE
(
SEE APPLICATION NOTE
FILM
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
Preliminary specification
SAA4996H
INTPOL
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0