w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 128

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
Type:
Bit Description:
WINBOND ELECTRONICS CORP. AMERICA
Bits [31:24]:
Bits [23:16]:
Bits 15:
Bits [14:13]
Bits [12:8]:
Bit 7:
Bit 6:
Bit 5:
Bits [4:0]:
Read/Write
Reserved. These bits are hardwired to a 0b.
User Defined. These bits are read/write and do not affect the operation of the W83C554F.
They can be used by the driver as a temporary storage. These bits will be 0b after reset.
1: Enable UltraDMA operation
0: Disable UltraDMA operation (default)
Set UltraDMA mode.
00: mode 0;
01: mode 1;
10: mode 2;
11: reserved
At 33MHz PCI clock, the high and low time of STROBE driven by 554F is:
Mode 0
Mode 1
Mode 2
CMD ON TIME. The value programmed to these bits controls the IDE_IOR# and IDE_IOW#
"ON" (low) time in clock cycles for this device. The actual number of clocks is the value
programmed plus one clock. The default value is 9h or 10 clocks. This value affects both PIO
and DMA timing.
PWEN. Posted write enable must be set to execute posted writes for this device. When this bit
is a 1b, posted writes are enabled. When this bit is a 0b, the default state, posted writes are
disabled. Only 32 bit cycles to an IDE data register will support posted write.
RDYEN. When set, the IDE_IOCHRDY signal from the IDE interface is enabled and can insert
wait states when this device is accessed. When 0, the IDE_IOCHRDY signal will have no effect
on accesses to this device. This bit will be 0b after a reset.
RAEN. Read-ahead enable must be enabled to execute read-ahead for this device. When this
bit is a 1b, read-ahead is enabled. When this bit is a 0b, the default state, read-ahead is
disabled. Only 32 bit cycles to an IDE data register will support read ahead.
CMD OFF TIME. The value programmed to these bits controls the IDE_IOR# and IDE_IOW#
"OFF" (high) time in clock cycles for this device. The actual number of clocks is the value
programmed plus one clock. The default value is 9h or 10 clocks. This value affects both PIO
and DMA timing.
STROBE High Time
120nS
75nS
60nS
STROBE Low Time
120nS
75nS
60nS
Register Information
126