w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 33

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
The PCI bus cycle can be split into two phases, the address phase and the data phase. The address phase of a PCI cycle is
defined as the first rising clock edge when FRAME# is asserted. On this clock edge, C/BE[3:0]# contains the bus command
that defines the PCI bus cycle, AD [31:0] contains a valid address, and IDSEL will be stable and valid if it is a configuration
cycle. All subsequent clocks comprise the data phase until the cycle is complete. If this cycle is claimed, DEVSEL# will be
asserted.
The next rising clock edge identifies the beginning of the data phase. Address parity is valid and will be checked or ignored
depending on the state of the SE bit of the Device Control Register. The data phase can last one or more clock cycles. Data
will be transferred on the rising clock edge when both IRDY# and TRDY# are asserted. Data parity will be generated (slave
I/O read or bus master memory write cycle) or checked (slave I/O write or bus master memory read cycle) on the next
rising clock edge. The W83C554F will report data parity errors on slave I/O write cycles it claims (by the assertion of
DEVSEL#) and bus master memory write cycles via the PERR# signal when enabled.
Normally for I/O cycles FRAME# will be de-asserted when IRDY# is asserted to signify that this is the last data transfer of
the data phase. STOP# will also be asserted with TRDY# to prevent I/O bursting. Multiple data phases (data bursting) are
supported when operating as a bus master.
WINBOND ELECTRONICS CORP. AMERICA
3.5
C/BE[3:0]# PCI Bus Cycle
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
PCI Bus Cycles
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Table 3-2 PCI Bus Cycles
Slave Mode
Supported
Supported
Supported
Supported
Ignored
Ignored
Supported
Supported
Ignored
Ignored
Supported
Supported
Supported (aliased to Memory Read)
Ignored
Supported (aliased to Memory Read)
Supported (aliased to Memory Write)
System Architecture
Master Mode
Not Generated
Not Generated
Not Generated
Not Generated
Not Generated
Not Generated
Supported
Supported
Not Generated
Not Generated
Not Generated
Not Generated
Supported
Not Generated
Supported
Supported
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