w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 69

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
AT System Control Register (default = 04h)
Type:
Bit Description:
WINBOND ELECTRONICS CORP. AMERICA
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Read/Write
Short ISA DMA. When this bit is set to "1", ISA DMA or Master cycles towards PCI will request
the PCI bus when the data towards PCI is ready. When this bit is set to "0", the ISA DMA or
Master cycles will start to request the PCI bus after DRQ is sampled active. (Default 0)
ISA Refresh Enable.
Reserved, always 0.
FERR# Enable. If this bit is set to "1," pin 12 will function as the Numeric Co-processor error
input.
Reserved.
P92E. Port 92 Enable. When enabled, access to Port 92 register in side 554F is enabled. The
cycle will be forward to the ISA bus. This is subtractive decode. . When disabled, cycle will be
passed to the ISA bus.
Keyboard RC Emulation Enable. In x86 mode, this bit decodes the keyboard reset command
and generates INIT for at more than 4 PCI clocks. In PowerPC mode, this bit decodes the
keyboard reset command and generates HRESET# for 1ms. In “test mode”, it will become 1us.
Keyboard Gate A20 Emulation Enable. This bit toggles the Gate A20 output in x86 mode,
depending on the keyboard command.
Short ISA DMA
Register Information
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