ppc440ep Applied Micro Circuits Corporation (AMCC), ppc440ep Datasheet - Page 77

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ppc440ep

Manufacturer Part Number
ppc440ep
Description
Powerpc 440ep Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet

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DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 9. DDR SDRAM Write Cycle Timing
AMCC Proprietary
440EP – PPC440EP Embedded Processor
MemClkOut0(90)
MemClkOut0
T
T
T
T
T
T
HD
SA
SD
DS
SK
HA
Addr/Cmd
MemData
PLB Clk
= Setup time for address and command signals to MemClkOut0(90)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
= Hold time for address and command signals from MemClkOut0(90)
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
DQS
T
SK
T
T
SA
HA
T
DS
T
SD
T
T
HD
DS
T
SD
T
HD
Revision 1.29 – May 07, 2008
Data Sheet
77

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