ppc440ep Applied Micro Circuits Corporation (AMCC), ppc440ep Datasheet - Page 83

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ppc440ep

Manufacturer Part Number
ppc440ep
Description
Powerpc 440ep Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet

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Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system
will still work, but there will be more latency before the data is sampled into RDSP. In this example, T
system dependent and taken into account by controller initialization software.
Figure 14. DDR SDRAM Read Cycle Timing—Example 3
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Read Clock Delayed
Data in Stage 1 D
Data out Stage 1
Data out Stage 3
DQS Stage 1 C
Data in at RDSP
Data out RDSP
Data out Stage 2
Data at pin
DQS at pin
PLB Clock
with ECC
with ECC
with ECC
T
DIN
High
Low
High
Low
High
Low
High
High
Low
Low
T
T
D0
SIN
T
T
P
TE
T
D0
= Propagation delay from Stage 2 input to RDSP input w/o ECC
= Propagation delay from Stage 2 input to RDSP input with ECC
D0
T
D1
P
D1
D0
D1
D2
D0
D2
D1
D2
D3
T
TE
D3
D2
D3
D0
D1
D3
D2
(3)
Revision 1.29 – May 07, 2008
D0
D1
Data Sheet
D2
D3
D0
D1
D2
D3
T
and T
D2
D3
TE
are
83

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