ppc440ep Applied Micro Circuits Corporation (AMCC), ppc440ep Datasheet - Page 81
ppc440ep
Manufacturer Part Number
ppc440ep
Description
Powerpc 440ep Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
1.PPC440EP.pdf
(87 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ppc440ep-3BB400C
Manufacturer:
AMCC
Quantity:
210
Company:
Part Number:
ppc440ep-3BC400C
Manufacturer:
AMCC
Quantity:
892
Company:
Part Number:
ppc440ep-3JC333C
Manufacturer:
AMCC
Quantity:
450
Company:
Part Number:
ppc440ep-3JC533C
Manufacturer:
FSC
Quantity:
21 400
Example 1:
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage
1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically
close to the PPC440EP, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary
to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example, T
system dependent and taken into account by controller initialization software.
Figure 12. DDR SDRAM Read Cycle Timing—Example 1
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Data in Stage 1 D
Data out Stage 1
Data in at RDSP
DQS Stage 1 C
Data out RDSP
with no ECC
Data at pin
DQS at pin
PLB Clock
T
DIN
High
Low
High
Low
T
High
Low
T
D0
SIN
T
D0
T
T
T
P
T
T
SIN
P
DIN
T
D0
= Propagation delay through FFs
= Propagation delay, Stage 1 input to RDSP input w/o ECC
= Delay from DQS at package pin to C on Stage 1 FF.
T
= Delay from data at package pin to D on Stage 1 FF.
D1
D0
P
D1
D0
D1
(1)
D0
D1
D2
D2
D0
D1
D2
D3
D2
D3
D2
D3
D2
D3
Revision 1.29 – May 07, 2008
D2
D3
Data Sheet
T
is
81