vp520s Mitel, vp520s Datasheet

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vp520s

Manufacturer Part Number
vp520s
Description
Pal/ntsc To Cif/qcif Converter
Manufacturer
Mitel
Datasheet
Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2
FEATURES
ASSOCIATED PRODUCTS
Lower Power, pin compatible replacement for VP520
Converts CCIR601 luminance and chrominance to CIF
or QCIF resolution, and vice versa, using a 27MHz
system clock.
Luminance and chrominance channels have their own
sets of horizontal and vertical filters with on chip line
stores
Each filter set may be configured to either decimate or
interpolate.
NTSC line insertion or removal mode
Produces / expects CIF/QCIF data in macroblock for-
mat.
120 Pin QFP Package
VP510 Colour Space Converter
VP2611 H261 Encoder
VP2615 H261 Decoder
VP2612 Video Multiplexer
VP2614 Video Demultiplexer
CHROMINANCE
LUMINANCE
8 BIT
8 BIT
HOST
BUS
CREF
MUXING
MUXING
COEFF
STORE
FILTER BLOCK
Fig 1 : Simplified Block Diagram
DELAYS
FILTER BLOCK
FILTER BLOCK
FOUR
LINE
Horizontal
Filters
DESCRIPTION
luminance and chrominance data between CCIR601 and CIF/
QCIF resolutions. Vertical and horizontal FIR filters are pro-
vided, with the vertical filters supported by on chip line stores.
The coefficients used by the filters are user definable, and are
down loaded from an independent host data bus. An internal
address generator supports an external DRAM frame store,
and also provides line to macroblock conversion.
precede the vertical filters, and are provided with between 8
and 16 taps. The vertical filters are provided with four CIF line
delays which allow a 5 tap filter to be implemented. When
producing QCIF the available RAM is used to provide six line
delays, which thus allows 7 tap filters to be used.
ing data must be in macroblock format, and the vertical filters
precede the horizontal filters The inputs are firstly written to a
external CIF sized frame store, and are read out in line format.
The VP520S will support two complete frame stores, and
allows the CIF/QCIF data to be read out twice in order to
produce two interlaced fields of video.
and NTSC video. An extra line is produced for every five lines
when producing CIF data, and one line in six is removed when
producing NTSC video. Poly phase filters are used to provide
the correct decimation and interpolation ratios.
Vertical
Filters
The VP520S is designed to convert 16 bit multiplexed
When producing CIF or QCIF video the horizontal filters
When the device is producing CCIR601 video, the incom-
The VP520S supports the conversion between CIF/QCIF
PAL/NTSC to CIF/QCIF Converter
MUX
OUTPUT
INPUT/
FIFO
LINE TO BLOCK
RAM ADDRESS
CONVERSION
GENERATOR
SUPPORTING
GENERATOR
Advance Information
SYNC
VP520S
DS3504 - 3.2 October 1996
VP520S
MACROBLOCK
MACROBLOCK
FRAME START
FRAME STORE
REQ BLKS
ADDRESS
CONTROL
STROBE
HREF
/ READY
VREF
16 BIT
8 BIT
BUS
BUS
VP520S
1

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vp520s Summary of contents

Page 1

... The inputs are firstly written to a external CIF sized frame store, and are read out in line format. The VP520S will support two complete frame stores, and allows the CIF/QCIF data to be read out twice in order to produce two interlaced fields of video. ...

Page 2

... The HBLANK output is then not defined. All data changes are referenced to the system clock. The edge actually used is indicated by the CREF input signal, which has a period of double the clock period. The VP520S will strobe in data on the rising edge of the system clock which occurs whilst CREF is high. ...

Page 3

... Cr Cb values by adding 128 to the results, regardless of the state of the Control Bit. COPING WITH SYNC JITTER When input syncs to the VP520S have jitter, due to the use of a composite video decoder which does not produce a line locked clock necessary to use an external FIFO line buffer ...

Page 4

... It takes the VP2611 almost exactly all the available time frame rates to process all the macroblocks. After a field time ( half an interlaced frame ) the VP520S will start to write new data to the DRAM, and data could be overwritten during the last macroblocks. Since there is available space in the DRAM, a small address offset is used between video fields to avoid this problem ...

Page 5

... If the VP520S is receiving frames at the full CIF 30 Hz frame rate but only displaying PAL frames at 25 Hz, then periodically one of the PAL frames ( comprising two interlaced fields will be generated from two received CIF/QCIF frames ...

Page 6

... CIF data frame rates. In the decode mode the VP520S produces two fields rates from every 30 Hz received frame, thus writing need only be half the rate of reading. In the decimate mode the VP520S produces a CIF frame using line rates which could have supported two 60Hz fields, but only one is used ...

Page 7

... VP520S 50-54 4, odd field 55-59 5, odd field 0-6 1, even field 7-13 2, even field 14-20 1, odd field 21-27 2, odd field 0-6 1, even field ...

Page 8

... Figures 7 and 8, and are optimal when the even field provides the original video assumed that one of the interlaced fields has been discarded prior to the VP520S, and thus no further decimation occurs when producing CIF luminance from PAL ( NTSC in 8 ...

Page 9

... Chrominance, however, is decimated by two. When produc- ing QCIF data the luminance channel is decimated by two, and the chrominance by four. When the VP520S is used to derive interlaced CCIR601 video, the internal address generator will read the CIF/QCIF frame store twice in order to produce the two fields. Each field has its own set of coefficients ...

Page 10

... VP520S QCIF LINES NTSC LINES LUM CHROM EVEN ODD Fig 9 : Interpolating from QCIF to NTSC 10 used in each set since six line delays are provided. The luminance filter conceptually contains 28 taps ( four sets of seven coefficients with two sets used to produce each field ). ...

Page 11

... Each luminance and chrominance set consists of seven coefficients, since six line delays are provided for the filters. JTAG Test Interface The VP520S includes a test interface consisting of a boundary scan loop of test registers placed between the pads and the core of the chip. The control of this loop is fully JTAG/ IEEE 1149-1 1990 compatible ...

Page 12

... STATIC ELECTRICAL CHARACTERISTICS Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current Input capacitance Output leakage current Output S/C current ORDERING INFORMATION VP520S/CG/GH1R (Commercial - Plastic QFP package) 12 Test -0.5V to 7.0V Delay from output high to output -0. 0.5V DD high impedance -0. ...

Page 13

... C2 HD5 VDD GND HD6 HD7 CLMP 70 94 N/C VDD 71 95 GND D15 72 96 VP520S FUNC PIN D14 97 D13 98 D12 99 GND 100 VDD 101 D11 102 D10 103 D9 104 D8 105 GND 106 VDD 107 D0 108 D1 109 D2 110 D3 111 ...

Page 14

... VP520S Signal Direction JTAG Bit Number A8 OUT 145 A7 OUT 144 OUT A6 143 A5 OUT 142 A4 OUT 141 A3 OUT 140 OUT A2 139 A1 OUT 138 A0 OUT 137 RW OUT 136 OUT RAS 135 dram_oeb OUT 134 M7 OUT 133 M7 IN 132 OUT M6 131 M6 IN 130 M5 OUT ...

Page 15

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Page 16

... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...

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