vp520s Mitel, vp520s Datasheet - Page 2

• Manufacturer Part Number: vp520s
• Description: Pal/ntsc To Cif/qcif Converter
• Manufacturer: Mitel

VP520S
PIN DESCRIPTION
NAME
Y7:0
C7:0
M7:0
D15:0
A7:0
A8
RAS
CAS
R/W
HREF
VREF
CREF
FREF
HBLNK
CSYNC
CLMP
VRST
FRST
REQYUV
MCLK
FSIG
SCLK
HD7:0
HA3:0
RD
WR
CEN
RST
TDI
TDO
TMS
TCK
TRST
TOE
NOTE:
"Barred" active low signals do not appear with a bar in the main
body of the text.
2
TYPE
I/O
I/O
I/O
I/O
O
O
O
O
O
I/O
I/O
I/O
I/O
O
O
O
I
I/O
I/O
I
I/O
I
I
I
I
I
I
O
I
I
I
I
FUNCTION
Luminance input or output bus
Chrominance input or output bus
Macroblock input or output bus
16 bit data bus for DRAM frame store
Multiplexed address bus to the DRAM
Most sig address bit or second CAS
Row strobe for the DRAM's
Column strobe for the DRAM's
Read/ write signal to the DRAM's
Horiz. reference in or horiz. sync out
Vertical reference in or vertical sync out
CREF in or CREF out
Field Indicator in or out
Horizontal Blanking output
Composite sync output in free run mode
Defines a black level clamping period
for A/D converters
Frame start identifier. If FRST is low
then a low going edge will reset the
internal sync generator.
Field identifier
Request macroblocks from encoder
Macroblock I/O strobe
Frame start/ ready signal
System Clock. 27MHz in PAL/NTSC
systems
Host data bus
Host controller address bits
An active low host read strobe
An active low host write strobe
An active low enable for the strobes
Power on reset
JTAG I/P data
JTAG O/P data
Test mode select
JTAG clock
JTAG reset
When high all O/P's are high
impedance
LUM
INPUT
CHROM
INPUT
CLOCK
CREF
INPUT
INPUT
HREF
INPUT
HBLNK
O/P
10ns min
Fig 2 : Luminance and chrominance inputs in the decimate mode.
PROGRAMMED DELAY
First Cr Comp.
10ns
10ns
min
min
10ns
min
First I/P
VIDEO COMPRESS MODE ( DECIMATE )
to CIF or QCIF spatial resolution prior to compression. Incom-
ing luminance and chrominance data does not need any prior
buffering, but must meet the timing requirements given in
Figure 2. A bit in Control register 1 allows the Cb component
to precede the Cr component if necessary. This data is passed
through vertical and horizontal decimating filters before it is
stored in an external frame store. When a complete field has
been decimated it is read out in macroblock format and
transferred to the next system component.
which are used to reference active video with respect to video
synchronization pulses. The active going edges are used
internally, and these must meet the set up time with respect to
the system clock as given in Figure 2. Stable inputs are
needed with no jitter due to asynchronous pixel clocks, but
when this is not possible an external FIFO can be used plus
two extra signals as described later. The reference inputs
need only stay active for one system clock period. Note that
the active going edges for HREF and VREF can individually
be defined to be high going or low going, through two bits in
Control Register 0. Also note that CREF is always an input and
is used as a qualifier for SCLK. The actual edges of CREF are
not used.
if there is a need to supply sync to the video source. The HREF
and VREF pins are then used to output HSYNC and VSYNC.
Composite sync is supplied on the CSYNC pin.
wide] which can be used to DC restore the black level in an A/
D converter. It is active high during the back porch.
the device expects the first pixel in a line to be supplied, and
is derived from the user supplied HREF input. The delay
between HREF and HBLANK is user definable in multiples of
CREF periods. If the defined value is zero then the HREF input
must be horizontal blanking with the minimum set time speci-
fied. The HBLANK output is then not defined.
edge actually used is indicated by the CREF input signal,
which has a period of double the clock period. The VP520S will
strobe in data on the rising edge of the system clock which
occurs whilst CREF is high.
2ns
min
2ns
min
2ns
min
This mode is used when CCIR601 video is to be converted
In this mode HREF, VREF, and FREF are normally inputs
The internal sync generator can still be used in this mode,
In addition the CLMP pin provides a pulse [13 SCLK's
The horizontal blanking output (HBLANK) defines when
All data changes are referenced to the system clock. The
First Cb Comp.
Second I/P