vp520s Mitel, vp520s Datasheet - Page 6

• Manufacturer Part Number: vp520s
• Description: Pal/ntsc To Cif/qcif Converter
• Manufacturer: Mitel

VP520S
using fast page mode in order to guarantee RAS precharge
times and RAS to CAS delays.
which meets real time CIF requirements. The exchange rate
with the encoder or decoder is only half of this, but is adequate
for CIF data at 30 Hz frame rates. In the decode mode the
VP520S produces two fields at 60 Hz rates from every 30 Hz
received frame, thus writing need only be half the rate of
reading. In the decimate mode the VP520S produces a CIF
frame using line rates which could have supported two 60Hz
fields, but only one is used. Thus reading rates need only be
half writing rates since the spare field time is available.
required, which dictates the use of 256K word DRAM's. The
A8 pin then provides the ninth address bit needed for such
devices. In the decimate mode only one CIF frame store is
required, and a Control Register Bit allows the user to select
either 256K word DRAM's, or 64K x 16 devices. In the latter
case two such devices are needed, and the A8 pin now
supplies a second CAS strobe to enable the second device.
Refresh cycles generate CAS before RAS sequences.
HOST INTERFACE
host interface using a data bus and an address bus. To
minimize on pin count the VP520S only uses four address
lines, and all internal RAM is addressed through counters. All
data is validated with a read or write strobe, and an active low
enabling signal. These strobes can be asynchronous to the 27
MHz clock, but the latter must be present to move the data
through several pipeline delays. Strobes must thus be valid for
several clock periods. Timing is shown in Figure 5.
must store 40 horizontal coefficients and 210 vertical coeffi-
cients. Internal storage must thus be provided for a total of 250
eight bit coefficients, and this is split into four blocks. These
consist of storage for 24 horizontal luminance coefficients;
storage for 16 horizontal chrominance coefficients; storage for
70 vertical luminance coefficients; and finally 140 vertical
chrominance coefficients. Each block of RAM has its own
internal address counter, and all counters are simultaneously
reset with a write to address F hex. Each RAM area has an
associated address as listed below, and a read or write using
that address will increment the relevant counter. Attempts to
use more addresses than are applicable to a particular area
will cause undefined behaviour.
Addr Function
0
1
2
3
4
5
6
7
8
6
The above time partitioning gives a line rate of 6.75 MHz,
In the interpolate mode two complete CIF frame stores are
The VP520S employs a conventional memory mapped
In the worst case mode ( QCIF to NTSC video ), the device
Address allocations are given below;
Reserved
R/W horizontal luminance coefficients. Max 24
R/W horizontal chrominance coefficients. Max 16.
Normally 00 Hex. When 02 Hex the sync generator can be
reset with the FRST and VRST pins.
Reserved for internal use
R/W vertical luminance coefficients. Max 70.
R/W vertical chrominance coefficients. Max 140.
Set to the normal operating value of 01 Hex by RESET. When
loaded with 21 Hex an encoding plus a decoding VP520S can
be connected 'back to back' for test purposes or coefficient
investigations. No other values must be used.
Control Register 0. See below.
9
A
A/B
C
D
E
F
and are defined below. Where necessary the action caused
when changing a control bit is delayed until the start of a new
field.
REGISTER 0 (Address 8)
BIT
0
1
2
3
4
5
6
7
REGISTER 1 (Address 9)
BIT
0
1
2
3
4
5
6
7
USE OF ADDRESS 7
connect the encoding and decoding filters into a back to back
configuration. This is useful for test purposes or for evaluating
the filter coefficient values, and it avoids the need for a 'Frame
Start' signal into the filter in the decode path. In normal
operation address 7 should contain 01 which is the default
after a reset operation.
LOADING COEFFICIENTS
for different modes. The filter sections below describe the use
of coefficient sets. Within a set, coefficients are stored in
ascending order, ie. C0, C1, C2 etc. Note that some locations
are shown as not used. However, since each store is loaded
sequentially, the data stream used to load the coefficient
stores must contain padding values corresponding to the
unused addresses. Note also that only the address range
shown in the tables have to be loaded with data.
By loading Hex 21 into host address 7 it is possible to
The following tables show the coefficient storage locations
The bits in control registers 0 and 1 are used individually,
Control Register 1. See below
Line delay from VREF to first active line. 6MSBs only
Pixel delay from HREF to first active pixel 2 Bits from A
plus 8 from B to give a 10 Bit value. Bit A1 is the MSB
Blanked screen Y value
Blanked screen U value
Blanked screen V value
Clear all address counters
FUNCTION
Interpolate if high, decimate if low
PAL if low, NTSC if high
QCIF if high, CIF if low
If low subtract 16 from Y, add 16 back after filtering
If low subtract 128 from chrominance I/Ps, add 128 to O/Ps
If low generate sync, if high lock to HREF and VREF
If low then active edge of VREF is low going.
If low then active edge of HREF is low going.
FUNCTION
If low then U inputs precede V inputs and outputs
If low use the internal field detect logic
Field Select. See text.
If low use 64Kx16 DRAM ( encoder only )
When high specifies Split Screen mode (encoder only)
When low the Frame Ready Flag is enabled
When high the screen is blanked (colour defined in addresses
C, D, E)
When high DRAM writes are disabled