k7r321884m Samsung Semiconductor, Inc., k7r321884m Datasheet - Page 11

• Manufacturer Part Number: k7r321884m
• Description: 1mx36-bit, 2mx18-bit Qdrtm Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R321884M
K7R323684M
AC TIMING CHARACTERISTICS
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
Clock
Clock Cycle Time (K, K, C, C)
Clock Phase Jitter (K, K, C, C)
Clock High Time (K, K , C, C)
Clock Low Time (K, K, C, C)
Clock to Clock (K
Clock to data clock (K
DLL Lock Time (K, C)
K Static to DLL reset
Output Times
C, C High to Output Valid
C, C High to Output Hold
C, C High to Echo Clock Valid
C, C High to Echo Clock Hold
CQ, C Q High to Output Valid
CQ, C Q High to Output Hold
C, High to Output High-Z
C, High to Output Low-Z
Setup Times
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
4. To avoid bus contention, at a given voltage and temperature tCHQX
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
2. Control signal are R and W.
3. If C,C are tied high, K, K become the references for C,C timing parameters.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
In case of BW
(0 C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70 C, 1.7V)
The specs as shown do not imply bus contention beacuse tCHQX
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER
0
,BW
K , C
1
(BW
C , K
2
, BW
C )
3
, also for x36) signal follow the data setup/hold times.
C )
SYMBOL
t
t
t
t
t
t
t
KC reset
t
t
t
t
CHCQV
CHCQX
CQHQV
CQHQX
t
t
t
t
t
KC lock
CHQX1
t
t
t
t
KC var
t
t
KHCH
CHQV
CHQX
CHQZ
KHKH
KHKL
KLKH
KHKH
AVKH
DVKH
KHAX
KHDX
IVKH
KHIX
(V
DD
=1.8V 0.1V, T
1024
-0.45
-0.45
-0.30
-0.45
4.00
1.60
1.60
1.80
0.00
0.50
0.50
0.35
0.50
0.50
0.35
MIN
30
-25
- 11 -
MAX
1
6.30
0.20
1.80
0.45
0.45
0.30
0.45
is a MIN parameter that is worst case at totally different test conditions
1Mx36 & 2Mx18 QDR
1
A
is bigger than tCHQZ.
=0 C to +70 C)
-0.45
-0.45
-0.35
-0.45
1024
5.00
2.00
2.00
2.20
0.00
0.60
0.60
0.40
0.60
0.60
0.40
MIN
30
-20
MAX
7.88
0.20
2.30
0.45
0.45
0.35
0.45
1024
-0.50
-0.50
-0.40
-0.50
6.00
2.40
2.40
2.70
0.00
0.70
0.70
0.50
0.70
0.70
0.50
MIN
30
-16
TM
MAX
8.40
0.20
2.80
0.50
0.50
0.40
0.50
II b4 SRAM
UNITS NOTES
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Dec. 2003
Rev 2.0
5
6
3
3
3
3
2
2