k7r321884m Samsung Semiconductor, Inc., k7r321884m Datasheet - Page 6

• Manufacturer Part Number: k7r321884m
• Description: 1mx36-bit, 2mx18-bit Qdrtm Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R321884M
Write Operations
Programmable Impedance Output Buffer Operation
Single Clock Mode
Depth Expansion
Power-Up/Power-Down Supply Voltage Sequencing
K7R323684M
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with K clock.
For 4-bit burst DDR operation, it will write four 36-bit or 18-bit or 8-bit data words with each write command.
The first "late" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
The process continues until all four data are transfered and registered.
Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
The device disregards input data presented on the same cycle W disabled.
When the W is disabled after a read operation, the K7R323684M and K7R321884M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
The K7R323684M and K7R321884M support byte write operations.
With activating BW
In K7R321884M, BW
And in K7R323684M BW
The K7R323684M and K7R321884M can be operated with the single clock pair K and K,
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
After power up, this device can’t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently
Before chip deselected, all read and write pending operations are completed.
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs"
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,
The following power-up supply voltage application is recommended: V
simultaneously, as long as V
removal sequence is recommended: V
does not exceed V
and read and write operation do not affect each other.
or other anomalous behavior in the SRAM.
the SRAM needs 1024 non-read cycles.
during operation.
insted of C or C for output clocks.
DD
0
or BW
resistor will give an output impedance of 50 .
0
by more than 0.5V during power-down.
controls write operation to D0:D8, BW
2
1
controls write operation to D18:D26, BW
( BW
DDQ
does not exceed V
2
or BW
IN
3 )
, V
in write cycle, only one byte of input data is presented.
REF
, V
DDQ
DD
, V
by more than 0.5V during power-up. The following power-down supply voltage
DD
, V
1
controls write operation to D9:D17.
SS
- 6 -
. V
1Mx36 & 2Mx18 QDR
3
DD
controls write operation to D27:D35.
SS
and V
, V
DD
DDQ
, V
DDQ
can be removed simultaneously, as long as V
, V
REF
, then V
SS
through a precision resistor(RQ).
IN
. V
DD
TM
and V
II b4 SRAM
DDQ
can be applied
Dec. 2003
Rev 2.0
DDQ