k7r321884m Samsung Semiconductor, Inc., k7r321884m Datasheet - Page 8

• Manufacturer Part Number: k7r321884m
• Description: 1mx36-bit, 2mx18-bit Qdrtm Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R321884M
TRUTH TABLES
K7R323684M
SYNCHRONOUS TRUTH TABLE
Notes: 1. X means "Don t Care".
WRITE TRUTH TABLE
Notes: 1. X means "Don t Care".
WRITE TRUTH TABLE
Notes: 1. X means "Don t Care".
Stopped
K
K
4. This table illustates operation for x18 devices.
2. The rising edge of clock is symbolized by (
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
3. Before enter into clock stop status, all pending read and write operations will be completed.
3. Assumes a WRITE cycle was initiated.
3. Assumes a WRITE cycle was initiated.
4. This signal was HIGH on previous K clock rising edge. Initating consecutive READ or WRITE operations on consecuti ve K clock rising edges
5. If this signal was LOW to inititate the previous cycle, this signal becomes a don t care for this operation however it is strongly recommended
K
that this signal is brought HIGH as shown in the truth table.
is not permitted. The device will ignore the second request.
H
L
R
H
X
4
5
K
W
L
H
X
X
4
K
(x18)
(x36)
Previous
at K(t+1)
D(A1)
state
Din
BW
X
X
H
H
H
H
H
H
L
L
L
L
0
Previous
at K(t+1)
BW
D(A2)
state
H
H
H
H
L
L
L
L
Din
X
X
0
BW
H
H
H
H
H
H
L
L
L
L
1
D
).
Previous
at K(t+2)
D(A3)
state
Din
X
X
BW
BW
L
L
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
1
2
Previous
at K(t+2)
D(A4)
state
Din
- 8 -
X
X
1Mx36 & 2Mx18 QDR
BW
H
H
H
H
H
H
L
L
L
L
3
Previous
at C(t+1)
High-Z
Q(A1)
D
state
OUT
X
Previous
at C(t+2)
High-Z
Q(A2)
D
state
WRITE ALL BYTEs ( K
WRITE ALL BYTEs ( K
WRITE NOTHING ( K
WRITE NOTHING ( K
OUT
WRITE BYTE 2 and BYTE 3 ( K
WRITE BYTE 2 and BYTE 3 ( K
X
WRITE BYTE 0 ( K
WRITE BYTE 0 ( K
WRITE BYTE 1 ( K
WRITE BYTE 1 ( K
WRITE ALL BYTEs ( K
WRITE ALL BYTEs ( K
WRITE NOTHING ( K
WRITE NOTHING ( K
OPERATION
Q
WRITE BYTE 0 ( K
WRITE BYTE 0 ( K
WRITE BYTE 1 ( K
WRITE BYTE 1 ( K
Previous
at C(t+2)
High-Z
Q(A3)
).
).
D
state
OPERATION
OUT
X
TM
Previous
at C(t+3)
High-Z
Q(A4)
state
D
OUT
X
II b4 SRAM
OPERATION
No Operation
Clock Stop
Read
Write
Dec. 2003
Rev 2.0