cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 62

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.6 ATM Cell Processing
2-28
2.6.1.2 Cell Generation
Interrupts for Transmit
Status and Status
Table 2-18. Overhead Field Locations
registers [0x04–0x07], disable the field generation and allow the existing field to
pass. Error HEC [bit 11] and Error Payload CRC [bit 12] force a single error
occurrence in the generated field. The Error functions are cleared after the error
is generated. This allows the microprocessor to easily generate a specific number
of errors. The error pattern programmed in the TXFEAC_ERRPAT register
[0x03] is used with the Error HEC control to generate a specific number of HEC
errors for checking receiver error correction/detection circuitry.
The Inhibit Single Cell Generation [bit 13] field in CELL_GEN_x, inhibits cell
transmission from the port for a single cell interval. A single idle cell (with header
contents as defined in the Transmit Idle Header Register [0x0A–0x0B] and
payload set to all 0s) is transmitted in place of a data cell from this port at the next
cell interval if the priority control tries to obtain a cell from this port. This bit is
cleared by the cell generation circuitry after the idle cell has been transmitted or if
a cell from another port is selected by the priority control. The microprocessor
can poll this bit to determine when the idle cell insertion has been completed.
header for idle cells is obtained from the TX_IDLE_xx registers, and the HEC is
automatically calculated. The payload for idle cells is obtained from the
IDLE_PAY register [0x2A]. This data octet is inserted in all octet positions of the
idle cell payload. The CRC-10 can be inserted if required by setting Disable
Payload CRC of CELL_GEN_x to zero.
A per-port count of cells transmitted is maintained in the CELL_SENT_CNTx
counters [0x4E–0x51] for each port. These counters can be programmed to cause
an interrupt in the CELL_STATUS register [0x3B] by setting enable bits in the
EN_CELL_INT register 0x30]. The interrupt clears when CELL_STATUS is
read. If the counter interrupt is not enabled, the counter stops at its maximum
value of 65,535. If the interrupt is enabled, the counter interrupts on “roll over”
and continues counting. The counter clears when it is read.
Cell Header
Header Error Control
Segment Type
Sequence Count
Length Field
Payload CRC
Disable HEC [bit 9] and Disable Payload CRC [bit 10] in the CELL_GEN_x
The Error Payload CRC bit inserts 4-bit errors into the payload CRC field.
Idle cells are automatically generated when no transmit port is active. The
Overhead Field
Conexant
Header Register TX_HDR or FIFO input
HEC Generation Circuit or FIFO input
FIFO Input
FIFO Input
FIFO Input
Payload CRC Generation Circuit or FIFO Input
ATM Transmitter/Receiver with UTOPIA Interface
Source
100046D
CN8223