cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 97

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
0x31—CONFIG_5 (Configuration Control Register 5)
The CONFIG_5 register is located at address 0x31 and controls miscellaneous functions. Bits 3–0 are control
bits which can be written and read. Bits 10, 9, and 8 are read-only status bits.
100046D
15–11
10
9
8
7
6
5
4
3
2
1
0
Bit
5
1
1
1
1
1
1
1
1
1
1
1
Field
Size
Reserved
Receive G1 Bit 5
Receive G1 Bit 6
Receive G1 Bit 7
Bt8222: Reserved
for Bt8222B and
higher including the
CN8223: Reset
Set G1 X Bits All-1s
Enable HDLC Data
Link
Reserved
Transmit G1 Bit 5
Transmit G1 Bit 6
Enable External
Signal Label
Transmit Clock
Select
Name
Set to 0.
Indicates the value of the RDI qualifier bit being received in the G1 octet of the
STS-3c/STM-1 frame. This bit would be used in conjunction with bit 4 in the
LINE_STATUS register [0x38] to determine the type of RDI (Path Yellow) being
received.
Indicates the value of the RDI qualifier bit being received in the G1 octet of the
STS-3c/STM-1 frame. This bit would be used in conjunction with bit 4 in the
LINE_STATUS register [0x38] to determine the type of RDI (Path Yellow) being
received.
Indicates the value of the RDI qualifier bit being received in the G1 octet of the
STS-3c/STM-1 frame. This bit would be used in conjunction with bit 4 in the
LINE_STATUS register [0x38] to determine the type of RDI (Path Yellow) being
received.
Set to 0.
In Bt8222 revision B and higher, this bit is a software reset. Writing this bit to 1 has
the same affect as high logic level on pin 118, RESET.
Sets the X bits in the G1 octet of the PLCP overhead to all 1s when this bit is high.
When this bit is low, the X bits will be all 0s.
Enables the internal HDLC data link receiver and transmitter. Programming for the
HDLC data link is described in
Set to 0.
Controls the transmission of the qualified RDI signals in the path status octet (G1) in
SONET/SDH modes. The value written to this bit will be placed in the corresponding
bit of the G1 octet.
Controls the transmission of the qualified RDI signals in the path status octet (G1) in
SONET/SDH modes. The value written to this bit will be placed in the corresponding
bit of the G1 octet.
Selects the source for the C2 octet in the path overhead for SONET/SDH formats.
When this bit is low, the C2 octet is internally generated. When this bit is high, the
C2 octet is obtained from the TXOVH inputs.
Selects the clock source for the transmitter circuitry. When this bit is low, the
transmit clock is from the TXCKI or TXCKI_HS± inputs. When this bit is high, the
transmit clock is from the RXCKI or RXCKI_HS± inputs to enable loop timing.
Conexant
Section
Description
2.8.
3.3 Configuration Control Registers
3.0 Registers
3-11