SST29EE512-70-4C-EH SST [Silicon Storage Technology, Inc], SST29EE512-70-4C-EH Datasheet - Page 3

• Manufacturer Part Number: SST29EE512-70-4C-EH
• Description: 512 Kbit (64K x8) Page-Write EEPROM
• Manufacturer: SST [Silicon Storage Technology, Inc]

512 Kbit Page-Write EEPROM
SST29EE512
Write Operation Status Detection
The SST29EE512 provides two software means to detect
the completion of a Write cycle, in order to optimize the sys-
tem Write cycle time. The software detection includes two
status bits: Data# Polling (DQ
end of write detection mode is enabled after the rising WE#
or CE# whichever occurs first, which initiates the internal
Write cycle.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ
When the SST29EE512 is in the internal Write cycle, any
attempt to read DQ
load cycle will receive the complement of the true data.
Once the Write cycle is completed, DQ
data. Note that even though DQ
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles after an interval of 1 µs. See Fig-
ure 7 for Data# Polling timing diagram and Figure 16 for a
flowchart.
Toggle Bit (DQ
During the internal Write cycle, any consecutive attempts to
read DQ
between 0 and 1. When the Write cycle is completed, the
toggling will stop. The device is then ready for the next
operation. See Figure 8 for Toggle Bit timing diagram and
Figure 16 for a flowchart. The initial read of the Toggle Bit
will typically be a “1”.
Data Protection
The SST29EE512 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
©2005 Silicon Storage Technology, Inc.
6
will produce alternating ‘0’s and ‘1’s, i.e., toggling
7
7
6
of the last byte loaded during the byte-
or DQ
)
7
)
6
. In order to prevent spurious
7
) and Toggle Bit (DQ
7
may have valid data
7
will show true
6
). The
3
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29EE512 provides the JEDEC approved optional
Software Data Protection scheme for all data alteration
operations, i.e., Write and Chip-Erase. With this scheme,
any Write operation requires the inclusion of a series of
three byte-load operations to precede the data loading
operation. The three-byte load sequence is used to initiate
the Write cycle, providing optimal protection from inadvert-
ent Write operations, e.g., during the system power-up or
power-down. The SST29EE512 is shipped with the Soft-
ware Data Protection disabled.
The software protection scheme can be enabled by
applying a three-byte sequence to the device, during a
page-load cycle (Figures 5 and 6). The device will then
be automatically set into the data protect mode. Any
subsequent Write operation will require the preceding
three-byte sequence. See Table 4 for the specific soft-
ware command codes and Figures 5 and 6 for the tim-
ing diagrams. To set the device into the unprotected
mode, a six-byte sequence is required. See Table 4 for
the specific codes and Figure 9 for the timing diagram. If
a Write is attempted while SDP is enabled the device
will be in a non-accessible state for ~ 300 µs. SST rec-
ommends Software Data Protection always be enabled.
See Figure 17 for flowcharts.
The SST29EE512 Software Data Protection is a global
command, protecting (or unprotecting) all pages in the
entire memory array once enabled (or disabled). Therefore
using SDP for a single Page-Write will enable SDP for the
entire array. Single pages by themselves cannot be SDP
enabled or disabled, although the page addressed during
the SDP write will be written.
Single power supply reprogrammable nonvolatile memo-
ries may be unintentionally altered. SST strongly recom-
mends that Software Data Protection (SDP) always be
enabled. The SST29EE512 should be programmed using
the SDP command sequence. SST recommends the SDP
Disable Command Sequence not be issued to the device
prior to writing.
DD
Power Up/Down Detection: The Write operation is
DD
is less than 2.5V.
S71060-09-000
Data Sheet
9/05