SST49LF004B-33-4C-WHE SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-WHE Datasheet - Page 13

• Manufacturer Part Number: SST49LF004B-33-4C-WHE
• Description: 4 Mbit Firmware Hub
• Manufacturer: SST [Silicon Storage Technology, Inc]

4 Mbit Firmware Hub
SST49LF004B
Firmware Memory Write Cycle
TABLE 5: F
©2006 Silicon Storage Technology, Inc.
FIGURE 5: F
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
LFRAME#
3-9
10
11
12
13
14
15
16
17
LAD[3:0]
1
2
LCLK
IRMWARE
IRMWARE
MADDR
RSYNC
START
MSIZE
IDSEL
Name
Field
DATA
DATA
TAR0
TAR1
TAR0
TAR1
M
EMORY
1110b
Start
M
EMORY
Field Contents
IDSEL
0000b
0000 (1 Byte)
0000 to 1111
1111 (float)
1111 (float)
W
LAD[3:0]
RITE
YYYY
ZZZZ
1110
ZZZZ
1111
0000
1111
A[27:24]
W
RITE
C
A[23:20] A[19:16]
YCLE
1
C
YCLE
OUT then Float
Float then OUT The
IN then Float
Float then IN
A[15:12]
W
Direction
MADDR
LAD[3:0]
AVEFORM
OUT
IN
IN
IN
IN
IN
IN
A[11:8]
13
A[7:4]
Comments
LFRAME# must be active (low) for the device to
respond. Only the last field latched before LFRAME#
transitions high will be recognized. The START field
contents (1110b) indicate a Firmware Memory Write
cycle.
Indicates which
respond. If the IDSEL (ID select) field matches the
value of ID[3:0], the device will respond to the mem-
ory cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
The MSIZE field indicates how many bytes will be
transferred during multi-byte operations. The device
only supports single-byte writes. MSIZE=0000b
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the host drives the bus to all '1's and
then floats the bus prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
cycle.
sync” (RSYNC) indicating that the device has received
the input data.
In this clock cycle, the
all '1's and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
The host resumes control of the bus during this cycle.
During this clock cycle, the device generates a “ready
A[3:0]
SST49LF004B
MSIZE
0000b
D[3:0]
DATA
SST49LF004B
D[7:4]
takes control of the bus during this
SST49LF004B
TAR0
1111b
Preliminary Specifications
Tri-State
TAR1
device should
RSYNC
0000b
S71307-02-000
drives the bus to
1307 F04.0
TAR
T5.0 1307
2/06