SST49LF004B-33-4C-WHE SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-WHE Datasheet - Page 8

• Manufacturer Part Number: SST49LF004B-33-4C-WHE
• Description: 4 Mbit Firmware Hub
• Manufacturer: SST [Silicon Storage Technology, Inc]

Preliminary Specifications
PIN DESCRIPTIONS
TABLE 1: P
©2006 Silicon Storage Technology, Inc.
Symbol
LCLK
LAD[3:0]
LFRAME# Frame
MODE
RST#
INIT#
ID[3:0]
GPI[4:0]
TBL#
WP#
R/C#
A
DQ
OE#
WE#
RES
V
V
NC
10
DD
SS
1. I = Input, O = Output
-A
7
-DQ
0
0
Output Enable
Pin Name
Clock
Address and
Data
Interface
Mode Select
Reset
Initialize
Identification
Inputs
General
Purpose Inputs
Top Block Lock
Write Protect
Row/Column
Select
Address
Data
Write Enable
Reserved
Power Supply
Ground
No Connection
IN
D
ESCRIPTION
Type
PWR
PWR
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
1
N/A
PP
Interface
X
X
X
X
X
X
X
X
X
LPC
N/A
X
X
X
X
X
X
X
X
X
X
X
X
X
Functions
To provide a clock input to the control unit.
The clock conforms to the PCI specification.
To provide LPC bus information such as addresses and command
inputs/outputs to memory.
To indicate start of a data transfer operation; also used to abort an LPC cycle in
progress.
This pin determines which interface is operational. When held high, programmer
mode is enabled and when held low, LPC mode is enabled. This pin must be set at
power-up or before returning from reset and must not change during device opera-
tion. This pin must be held high (V
pin is internally pulled-down with a resistor between 20-100 KΩ.
To reset the operation of the device
This is the second reset pin for in-system use.
This pin functions identically to RST#.
These four pins are part of the mechanism that allows multiple parts to be attached
to the same bus. The strapping of these pins is used to identify the component. The
boot device must have ID[3:0]=0000, all subsequent devices should use sequential
count-up strapping. These pins are internally pulled-down with a resistor between
20-100 KΩ.
These individual inputs can be used for additional board flexibility. The state of these
pins can be read through GPI_REG (General Purpose Inputs Register). These
inputs should be at their desired state before the start of the LPC clock cycle during
which the read is attempted, and should remain in place until the end of the Read
cycle. Unused GPI pins must not be floated.
When low, prevents programming to the boot block sectors at the top of the device
memory. When TBL# is high it disables hardware write protection for the top block
sectors. This pin cannot be left unconnected.
When low, prevents programming to all but the highest addressable blocks. When
WP# is high it disables hardware write protection for these blocks. This pin cannot be
left unconnected.
Select for the Programming interface, this pin determines whether the address pins
are pointing to the row addresses, or to the column addresses.
Inputs for low-order addresses during Read and Write operations. Addresses are
internally latched during a Write cycle. For the programming interface, these
addresses are latched by R/C# and share the same pins as the high-order address
inputs.
To output data during Read cycles and receive input data during Write cycles. Data is
internally latched during a Write cycle.
The outputs are in tri-state when OE# is high.
To gate the data output buffers.
To control the Write operations.
These pins must be left unconnected.
To provide power supply (3.0-3.6V)
Circuit ground (0V reference)
Unconnected pins.
8
IH
) for PP mode and low (V
4 Mbit Firmware Hub
SST49LF004B
IL
) for LPC mode. This
S71307-02-000
T1.2 1307
2/06