SST49LF020A-33-4C-NHE SST [Silicon Storage Technology, Inc], SST49LF020A-33-4C-NHE Datasheet - Page 13

• Manufacturer Part Number: SST49LF020A-33-4C-NHE
• Description: 2 Mbit LPC Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

2 Mbit LPC Flash
SST49LF020A
TABLE 6: LPC Write Cycle
©2006 Silicon Storage Technology, Inc.
LFRAME#
LAD[3:0]
FIGURE 6: LPC Write Cycle Waveform
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
LCLK
3-10
CE#
11
12
13
14
15
16
17
1
2
CYCTYPE +
ADDRESS
START
Name
SYNC
Field
DATA
DATA
TAR0
TAR1
TAR0
TAR1
DIR
1 Clock 1 Clock
Start
0000b
CYCTYPE
011Xb
DIR
Field Contents
+
1111 (float)
1111 (float)
LAD[3:0]
A[31:28] A[27:24]
YYYY
ZZZZ
011X
0000
ZZZZ
1111
0000
1111
1
A[23:20]
Load Address in 8 Clocks
OUT then Float
Float then OUT The SST49LF020A takes control of the bus during this
IN then Float
Float then IN
Address
A[19:16]
Direction
LAD[3:0]
OUT
IN
IN
IN
IN
IN
A[15:12]
13
A[11:8]
Comments
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized.
Indicates the type of cycle. Bits 3:2 must be “01b” for
memory cycle. Bit 1 indicates the type of transfer “1”
for Write. Bit 0 is reserved.
Address Phase for Memory Cycle. LPC protocol sup-
ports a 32-bit address phase. YYYY is one nibble of
the entire address. Addresses are transferred most-
significant nibble first. See Table 3 for address bits def-
inition and
This field is the least-significant nibble of the data byte.
This field is the most-significant nibble of the data byte.
In this clock cycle, the host has driven the bus to all ‘1’s
and then floats the bus. This is the first part of the bus
“turnaround cycle.”
cycle.
The SST49LF020A outputs the values 0000, indicat-
ing that it has received data or a flash command.
bus to all ‘1’s and then floats the bus. This is the first
part of the bus “turnaround cycle.”
Host resumes control of the bus during this cycle.
In this clock cycle, the SST49LF020A has driven the
A[7:4]
A[3:0]
Table 4
Load Data in 2 Clocks
Data
D[3:0]
for valid memory address range.
D[7:4]
Data
TAR0
1111b Tri-State
2 Clocks
TAR1
1 Clock
S71206-08-000
0000b
Sync
Data Sheet
1206 F07.0
TAR
T6.0 1206
5/06