bt8375kpf Conexant Systems, Inc., bt8375kpf Datasheet - Page 112

• Manufacturer Part Number: bt8375kpf
• Description: Single Chip Transceivers For T1/e1 And Integrated Service Digital Network Isdn Primary Rate Interfaces Systems
• Manufacturer: Conexant Systems, Inc.

2.0 Circuit Description
2.10 Microprocessor Interface
2.10.1 Address/Data Bus
2.10.2 Bus Control Signals
2.10.3 Interrupt Requests
2-84
In Non-multiplexed Address mode, A[8:0] provides the address for register
access; in Multiplexed Address mode, A[8] and AD[7:0] provide the address. In
both modes, the data bytes flow over the shared bidirectional, byte-wide bus,
AD[7:0].
Four signals control the operation of the interface port: AS*, CS*, RD*, and
R/W*. An additional pin, MOTO*, selects whether the interface signals are of a
Motorola or Intel flavor.
and DS* signals are expected. When MOTO* is high, indicating an Intel-style
interface, CS*, ALE, RD*, and WR* signals are expected.
pin is usually tied high for Intel devices, and low for Motorola devices. SYNCMD
puts the interface into the Synchronous Processor Interface mode. Motorola
68000 processors typically have SYNCMD tied high if MCLK is connected to the
MPU clock source, while Intel 8051 processors have SYNCMD tied low (see
Table
Table 2-24. Microprocessor Interface Operating Modes
The INTR* output is an active low, open-drain type output which allows the
interrupt request line from multiple devices to connect to a common
microprocessor interrupt request line. All the Bt8370/8375/8376 interrupts are
requested on this pin. However, each interrupt source can be individually enabled
or disabled.
registers:
When MOTO* is low, indicating a Motorola-style interface, CS*, AS*, R/W*,
When MOTO* is high, the address lines are multiplexed with the data. This
Interrupts are associated with three types of microprocessor interface
• Interrupt Enable register—a 1 in a given bit of IER[7:0] enables the
• Interrupt Status register [ISR; 7:0]—events are latched into these registers
• Interrupt Request register [IRR; addr 003]—reading this register along
MOTO*
2-24).
0
0
1
1
corresponding interrupt, a 0 (initial condition) disables it.
whether the corresponding interrupt enable bit is set or not. The processor
must read the ISR registers to clear all latched bits.
with the corresponding ISR register, the microprocessor can determine the
cause of an interrupt. Active interrupts are indicated by bits that are high.
Inactive interrupts are indicated by bits that are low. Reading from IRR
clears the entire register; writing has no effect.
SYNCMD
Conexant
0
1
0
1
CLKMD
Fully Integrated T1/E1 Framer and Line Interface
0
1
0
1
Asynchronous Motorola, internal clock
Synchronous Motorola, external clock
Asynchronous Intel, internal clock
Synchronous Intel, external clock
Description
Bt8370/8375/8376
N8370DSE