bt8375kpf Conexant Systems, Inc., bt8375kpf Datasheet - Page 251

• Manufacturer Part Number: bt8375kpf
• Description: Single Chip Transceivers For T1/e1 And Integrated Service Digital Network Isdn Primary Rate Interfaces Systems
• Manufacturer: Conexant Systems, Inc.

Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
RSIG_AB/EMFBIT
RIDLE
SIG_STK
N8370DSE
180–19F— Receive Per-Channel Control (RPCn; n = 0 to 31)
RSIG_AB/
EMFBIT
7
AB Signaling (Per-Channel RSIG_AB [without DEBOUNCE])—In E1 mode, received
signaling is placed into RSIGn, but RSIGO output duplicates the buffered AB bit value in the
CD output bits, thus sending ABAB on RSIGO instead of ABCD. In T1 mode, RSIG_AB
instructs the receiver to use the available RSIGn buffer space to meet PUB43801 and
TR-170—which require three SF multiframes of receive signaling buffer storage before
output. Every 24 frames, the received ABCD signaling value is transferred from the RSIGn
input buffer space to the RSIGn output buffer space, regardless of whether the receiver
operates in SF, SLC, or ESF mode. In SF mode, the ABCD value contains AB = AB(N–1), and
CD = AB(N) from two multiframes. Since multiframe N–1 is the older sample, AB(N–1)
replaces AB(N) in the event of signaling freeze. RSIGO and RPCMO signaling bit output
values are always taken from RSIGn output buffer according to RSB frame number.
input buffer update mechanism by comparing—on a bit-by-bit basis—the present received
input signaling bit value with the current buffered signaling bit values from two prior
multiframes. If signaling from prior multiframe (N) differs from input and input equals
buffered value from two multiframes prior (N–1), the signaling bit value from multiframe N is
inverted when the input buffer is updated.
EMFBIT replaces all embedded F-bit outputs on RPCMO with the programmed value.
Time Slot Idle—When RIDLE is active, the incoming RX time slot data is only updated in
RSLIP_HIn buffer, and the RSB time slot data output is only extracted from RSLIP_LOn
buffer. Thus, the processor can write an 8-bit idle code pattern in RSLIP_LOn buffer for output
during RSB time slot.
Receive Signaling Stack—Selects whether changes detected in the ABCD signaling value are
reported in the signaling stack [addr 0DA]. Signaling for all time slots is continuously updated
in RSIGn buffer, regardless of the SIG_STK setting.
RIDLE
AB Signaling (Per-Channel RSIG_AB [with DEBOUNCE])—Debounce affects RSIGn
When RIDLE is active in an unassigned time slot defined to carry embedded F-bits,
6
SIG_STK
Sig Input
5
0
0
0
0
1
1
1
1
0 = normal ABCD and embedded F-bit throughput
1 = AB signaling and embedded F-bit replacement
0 = no effect
1 = RSB time slot replaced by contents of RSLIP_LOn
0 = no effect
1 = signaling stack
Buffer N, N-1
RLOCAL
4
Conexant
00
01
10
11
00
01
10
11
Update N, N-1
RSIGA
3
00
00
00
01
10
11
11
11
RSIGB
Change Update
Change Update
2
Debounce
Debounce
Notes
—
—
—
—
3.17 System Bus Registers
RSIGC
1
RSIGD
0
3-133