ST16C2550CQ48 EXAR [Exar Corporation], ST16C2550CQ48 Datasheet - Page 14

• Manufacturer Part Number: ST16C2550CQ48
• Description: 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
2.10.1
Receive Holding Register (RHR) - Read-Only
F
IGURE
Receive Data
Byte and Errors
16 bytes by 11-bit
F
IGURE
16X Clock
10. R
wide FIFO
16X Clock
and Errors
9. R
Data Byte
Receive
ECEIVER
ECEIVER
Receive Data Shift
O
Register (RSR)
PERATION IN
O
LSR bits
RX FIFO
Tags in
Error
PERATION IN NON
4:2
RHR
Receive Data Shift
Register (RSR)
Holding Register
Receive Data
FIFO M
Validation
Data Bit
(RHR)
14
ODE
-FIFO M
Validation
RHR Interrupt (ISR bit-2) when FIFO fills
up to trigger level.
FIFO is Enabled by FCR bit-0=1
Data Bit
ODE
RHR Interrupt (ISR bit-2)
Receive Data Characters
Receive Data Characters
RXFIFO1
RXFIFO1
xr
REV. 4.4.0