ST16C2550CQ48 EXAR [Exar Corporation], ST16C2550CQ48 Datasheet - Page 8

no-image

ST16C2550CQ48

Manufacturer Part Number
ST16C2550CQ48
Description
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST16C2550CQ48
Manufacturer:
MACNICA
Quantity:
1 000
Part Number:
ST16C2550CQ48
Manufacturer:
ST
0
Part Number:
ST16C2550CQ48
Manufacturer:
MACNICA
Quantity:
20 000
Part Number:
ST16C2550CQ48-F
Manufacturer:
EXAR
Quantity:
4 800
Part Number:
ST16C2550CQ48-F
Manufacturer:
EXAR22
Quantity:
250
Part Number:
ST16C2550CQ48-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
ST16C2550CQ48-F
Manufacturer:
ST
0
Part Number:
ST16C2550CQ48-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Part Number:
ST16C2550CQ48-F
0
Part Number:
ST16C2550CQ48TR
Manufacturer:
EXAR
Quantity:
49
Part Number:
ST16C2550CQ48TR
Manufacturer:
ST
Quantity:
20 000
Part Number:
ST16C2550CQ48TR-F
Manufacturer:
EXAR
Quantity:
2 400
ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The C2550 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels
share the same data bus for host operations. The data bus interconnections are shown in
.
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
function in the device.
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
1.
CPU Interface
Device Reset
Channel A and B Selection
Table
F
IGURE
UART_RESET
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
11). An active high pulse of at least 40 ns duration will be required to activate the reset
RXRDYA#
RXRDYB#
TXRDYA#
TXRDYB#
3.
IOW#
IOR#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
ST16C2550 D
CSA#
1
0
1
0
T
ABLE
ATA
B
1: C
CSB#
US
1
1
0
0
I
HANNEL
NTERCONNECTIONS
8
Channel A and B selected
A
IOR#
IOW#
CSA#
CSB#
RESET
D0
D1
D2
D3
D4
D5
D6
D7
INTA
INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
A0
A1
A2
AND
Channel A selected
Channel B selected
UART de-selected
F
B S
UNCTION
Channel A
Channel B
UART
UART
ELECT
DTRA#
DSRA#
DTRB#
DSRB#
RTSA#
CTSA#
RTSB#
CTSB#
OP2A#
CDA#
OP2B#
CDB#
GND
VCC
RIA#
RIB#
TXA
RXA
TXB
RXB
VCC
Serial Interface of RS-
Serial Interface of
RS-232, RS-485
232, RS-485
Figure
2750int
xr
3.
REV. 4.4.0

Related parts for ST16C2550CQ48