sii1162 Silicon image, sii1162 Datasheet
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Technology SiI 1162 PanelLink Transmitter Data Sheet Document # SiI-DS-0081-B ® ...
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... Silicon Image. Inc. ® and the PanelLink trademark of Philips Semiconductor. Intel ECN Comment First Release. SiI1162CSU Universal part added; Fig 13,14,16 fixed; 200400290 JEDEC Pkg code updated; Part marking spec updated; Pin 24 (CTL3/A1) fix clarification for I C mode. I clarified. ...
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SiI 1162 PanelLink Transmitter Data Sheet General Description ..................................................................................................................................... 1 SiI 1162 Pin Diagram .................................................................................................................................. 1 Functional Block Diagram ........................................................................................................................... 1 PanelLink TMDS Digital Core ..................................................................................................................... Interface, Registers and Configuration Logic ....................................................................................... 1 Data Capture Logic ...
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Table 1. 12-bit Mode Data Mapping ............................................................................................................... 1 Table 2. DK[1:0] Increments and Effect on Setup and Hold times................................................................ 1 Table 3. Sample Programming Sequence for SiI 1162.................................................................................. 1 Table 4. Recommended Components............................................................................................................ 1 Table 5. Routing Guidelines for DVI ...
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SiI 1162 PanelLink Transmitter Data Sheet General Description The SiI 1162 transmitter uses PanelLink technology to support displays ranging from VGA to UXGA resolutions in a single link interface. The SiI 1162 transmitter uses a 12-bit interface, taking in one ...
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... C mode, de-skew pins DK0 and DK1 can be set to adjust the setup and hold times to the SiI 1162 by In non-I pull-up or pull-down resistors. The CTL3 pin can also be used for backward compatibility with older Silicon Image devices. The PD# pin can be used in non-I ...
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SiI 1162 PanelLink Transmitter Data Sheet Electrical Specifications Absolute Maximum Conditions Absolute Maximum Conditions are defined as the worst-case condition the part will tolerate without sustaining damage. Permanent device damage may occur if absolute maximum conditions are exceeded. Proper operation ...
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DC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter V Differential Voltage OD Single ended peak to peak amplitude V Differential High-level Output DOH 1 Voltage V Input Reference Voltage REF I Differential Output Short DOS 1 Circuit ...
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SiI 1162 PanelLink Transmitter Data Sheet AC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter T IDCK Period CIP F IDCK Frequency CIP T IDCK High Time CIH T IDCK Low Time CIL S Differential Swing Low-to- LHT ...
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Input Timing Diagrams V IH Figure 3. Clock Cycle/High/Low Times in High Swing Mode VSYNC, HSYNC CIP T CIH CIL S S LHT HLT 80 20% ...
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SiI 1162 PanelLink Transmitter Data Sheet IDCK+ Differential Clock D[11:0], DE, VSYNC, HSYNC Figure 7. Low Swing Control and Data Setup/Hold Times to IDCK+ Differential Clock Note that VREF is set Low Swing Mode. DDQ IDCK+ ...
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Data Mapping D[11: IDCK+ IDCK+ IDCK- IDCK+ IDCK+ IDCK- First Latch Edge Figure 11. Logical Interface Options for 12-bit Mode Pin Name Low D11 G0[3] D10 G0[2] D9 G0[1] D8 G0[0] D7 B0[7] ...
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SiI 1162 PanelLink Transmitter Data Sheet Data De-skew Input clock to data setup/hold time can be adjusted through the use of the de-skew feature. It should be noted that it is the clock that is being adjusted internally. The configuration ...
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Pin Descriptions Input Pins Pin Name Pin # Type 12-bit pixel bus input This bus inputs one-half pixel (12-bits) at every latch both falling and rising edge of the clock ...
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SiI 1162 PanelLink Transmitter Data Sheet Configuration/Programming Pins Pin Name Pin # Type ISEL/RST SCL/DK1 27 In SDA/DK0 26 In EDGE/HTPLG 44 In SiI -DS-0081-B Description Interface Select HIGH, then the I C ...
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Input Voltage Reference Pin Pin Name Pin # Type VREF 2 Analog In Power Management Pin Pin Name Pin # Type PD Differential Signal Data Pins Pin Name Pin # Type TX0+ 36 Analog TX0- 35 Analog TX1+ ...
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... R/W registers do not retain their value after a reset, but are set back to the default values shown in the table. 4. Registers and bits listed as RSVD are reserved and for Silicon Image, Inc. use only. 5. Default setting for the VDJK register 0x0C is 0x89, which is optimum for most applications. ...
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I C Register Definitions Register Name Access Description RO Vendor ID Low byte (0x01) VND_IDL RO Vendor ID High byte (0x00) VND_IDH RO Device ID Low byte (0x06) DEV_IDL RO Device ID High byte (0x00) DEV_IDH RO Device Revision ...
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SiI 1162 PanelLink Transmitter Data Sheet Slave Interface The SiI 1162 slave state machine does not require an internal clock and supports only byte read and write. Page mode is not supported. The 7-bit binary address of ...
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Enabling Hot Plug Detection Mode As documented in the VESA Digital Flat Panel Standard, all monitors are required to support Hot Plug Detection but support is optional for the host. The SiI 1162 supports the Hot Plug Detect feature. In ...
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SiI 1162 PanelLink Transmitter Data Sheet Design Recommendations 2 1. Bus Level-Shifting 2 To program the SiI 1162 via I C mode, SDA and SCL swing level must be 3.3V. DVO sources have I 1.5V. To ...
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Voltage Ripple Regulation The power supply to VCC pins is very important to the proper operation of the transmitter. Two examples of regulators are shown in Figure 17 and Figure 18. Vin=5V Figure 17. Voltage Regulation using TL431 Vin=5V Figure ...
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SiI 1162 PanelLink Transmitter Data Sheet PCB Ground Planes All ground pins on the device should be connected to the same, contiguous ground plane in the PCB. This helps to avoid ground loops and inductances from one ground plane segment ...
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Series Damping Resistors on Parallel Inputs Series resistors (22 Ω Ω ) are effective in lowering the data-related emissions and reducing reflections. Series resistors should be placed as close as possible to the D[11:0], HSYNC, VSYNC, DE and ...
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... TMDS signals at high frequencies(beyond 135MHz). The impact on DVI compliant receivers is minimal. Therefore Silicon Image recommends source termination for most applications. Note that the capacitor is required to meet DVI idle mode DC offset requirements and must not be omitted. Note also that the signal ...
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Transmitter Layout The routing for the SiI 1162 chip is relatively simple since no spiral skew compensation is needed. However, a few small precautions are required to achieve the full performance and reliability of DVI. The Transmitter can be placed ...
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SiI 1162 PanelLink Transmitter Data Sheet In addition to following the trace routing recommendations, length differences between intra-pair traces listed in column 2 of Table 5 and inter-pair traces listed in column 3 of Table 5, should be controlled to ...
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Recommended Circuits Note that the Hot Plug pin on the DVI connector will output a voltage up to 5V. A level-shifting circuit as illustrated in Figure 27 is needed to connect to the HTPLG pin on the SiI 1162, as ...
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SiI 1162 PanelLink Transmitter Data Sheet Packaging E-pad Enhancement The SiI 1162 is packaged in a 48-pin TSSOP package with E-pad. The E-pad dimensions are shown in Figure 28. P The E-pad is designed to allow better heat dissipation, and ...
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... Based on this discussion clear that designing a thermal landing area on the PCB for use with the SiI 1162 part is rarely necessary, but could be considered for applications where unanticipated extremes might be encountered. Operating outside of chip specifications is not recommended; contact your Silicon Image representative for analysis of non-standard operational requirements. ...
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... Body Thickness 0.95 D1 Body Size 9.70 E1 Body Size 4.40 4.50 E Footprint 6.40 L1 Lead Length 0.95 b Lead Width 0.23 c Lead Thickness 0.20 e Lead Pitch 0.40 Dimensions in millimeters. Overall thickness A=A1+A2. Lead length L1 = (E-E1)/2. Device Device Number SiI1162 Standard Pb-Free SiI1162U Legend Description LNNNNN.LLL Lot Number YY Year of Mfr WW Week of Mfr N.N Revision Number LLLLLLL Country of Packaging ...
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... Silicon Image. Inc. Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94085 USA SiI 1162 PanelLink Transmitter Tel: (408) 616-4000 Fax: (408) 830-9530 E-mail: salessupport@siimage.com Web: www.siliconimage.com 28 Data Sheet SiI -DS-0081-B ...