sii1162 Silicon image, sii1162 Datasheet - Page 18

• Manufacturer Part Number: sii1162
• Description: Panellink Transmitter
• Manufacturer: Silicon image

I
Register Name
Note that the VND_ID, DEV_ID and DEV_REV fields are identical to the values in the SiI 164 transmitter. This
provides backward compatibility with earlier BIOS and driver support. No changes are needed for the SiI 1162.
2
C Register Definitions
FRQ_HIGH
FRQ_LOW
MSEL[2:0]
DEV_REV
VND_IDH
VND_IDL
DEV_IDH
DEV_IDL
CTL[3:0]
DK[1:0]
HTPLG
VLOW
EDGE
RSEN
VDJK
TSEL
HEN
VEN
PD#
MDI
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Description
Vendor ID Low byte (0x01)
Vendor ID High byte (0x00)
Device ID Low byte (0x06)
Device ID High byte (0x00)
Device Revision (0x00)
Low frequency limit in Megahertz. (0x20). IDCK frequency limit.
High frequency limit minus 65MHz in Megahertz. (0x64). IDCK frequency limit.
Horizontal Sync Enable:
Vertical Sync Enable:
Edge Select (same function as EDGE pin)
Power Down mode (same function as PD# pin)
Voltage Swing Mode
Select source of the MSEN output pin
Interrupt Generation Method
This bit is HIGH if a powered on receiver is connected to the transmitter outputs, LOW
otherwise. This function is only available for use in DC-coupled systems.
Hot Plug Detect input, the state of HTPLG pin can be read from this bit.
Monitor Detect Interrupt:
De-Skewing Setting (Always enabled in I
General Purpose bits. (Default after RESET = 0x0)
VDJK register should be programmed to 0x89.
0 – HSYNC input is transmitted as fixed LOW
1 – HSYNC input is transmitted as is (Default after RESET)
0 – VSYNC input is transmitted as fixed LOW
1 – VSYNC input is transmitted as is (Default after RESET)
0 –Falling edge latched first in dual edge mode (Default after RESET)
1 –Rising edge latched first in dual edge mode
0 – Power Down (Default after RESET)
1 – Normal operation
0 – VREF signal indicates low swing inputs
1 – VREF indicates high swing inputs
0 – Interrupt bit (MDI) is generated by monitoring RSEN (Default after RESET)
1 – Interrupt bit (MDI) is generated by monitoring HTPLG
0 – Detection signal has changed logic level (write one to this bit to clear)
1 – Detection signal has not changed state
000 – Force MSEN outputs high (disabled) (Default after RESET)
001 – Outputs the MDI bit (interrupt)
010 – Outputs the RSEN bit (receiver detect)
011 – Outputs the HTPLG bit (hot plug detect)
1XX – Reserved
00 – Default Setting (Default after RESET with ISEL/RST#=HIGH)
01 – Maximum Hold time
10 – Maximum Setup time
11 – No Effect
14
2
C mode):
SiI 1162 PanelLink Transmitter
SiI -DS-0081-B
Data Sheet