sii1162 Silicon image, sii1162 Datasheet - Page 20

• Manufacturer Part Number: sii1162
• Description: Panellink Transmitter
• Manufacturer: Silicon image

Enabling Hot Plug Detection Mode
As documented in the VESA Digital Flat Panel Standard, all monitors are required to support Hot Plug Detection
but support is optional for the host. The SiI 1162 supports the Hot Plug Detect feature. In I
HTPLG input. It should be noted that the HTPLG pin on the SiI 1162 is only 3.3V tolerant therefore HTPLG
voltage level from the DVI connector should be level shifted or clamped at 3.3V.
When the voltage level at the HTPLG pin is 3.3V, the HTPLG bit will be set to 1. To output the HTPLG bit via the
MSEN pin, register bits MSEL [2:0] should be programmed to 0b011.
The SiI 1162 can also be programmed to enable the Hot Plug Detection Mode via the Receiver Sense function. In
this mode, HTPLG pin is not required. By programming MSEL [2:0] to 0b010, SiI 1162 will output the RSEN bit
state though the MSEN pin when the SiI 1162 is connected to a powered receiver.
RESET Description
The input pin ISEL/RST# serves as an asynchronous RESET (active LOW) for the I
mode. The programming registers that are accessible over the I
and after the RESET. Register bits PD# and MSEL[2:0] are both disabled after RESET. The minimum low time for
proper RESET is T
•
•
After a RESET, the SiI 1162 will be turned OFF. When RESET is asserted, the SiI 1162 power down
control bit, PD#, is forced to 0. When the SiI 1162 comes out of RESET (ISEL/RST# is set HIGH), the
SiI 1162 will be turned OFF. To turn the SiI 1162 back ON, the PD# bit must be set to 1 over the I
After a RESET, MSEN output is disabled. When RESET is asserted, MSEN [2:0] is forced to ‘000’. This
causes the MSEN output to be tri-stated.
RESET
. The state of these bits is set during the RESET period according to the following rules:
16
2
C bus do not retain their previous values during
SiI 1162 PanelLink Transmitter
2
C slave controller in I
2
C mode, use the
SiI -DS-0081-B
Data Sheet
2
C bus.
2
C