M48T37 ST Microelectronics, M48T37 Datasheet

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M48T37

Manufacturer Part Number
M48T37
Description
3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
Manufacturer
ST Microelectronics
Datasheet

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Table 1. Signal Names
February 2000
A0-A14
DQ0-DQ7
RST
IRQ/FT
WDI
E
G
W
V
V
NC
INTEGRATED ULTRA-LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION
YEAR 2000 COMPLIANT
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WATCHDOG TIMER
WRITE PROTECT VOLTAGE
(V
– M48T37Y: 4.2V
– M48T37V: 2.7V
PACKAGING INCLUDES a 44-LEAD SOIC and
SNAPHAT TOP (to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACKED-UP
BATTERY LOW FLAG
CC
SS
PFD
= Power-Fail Deselect Voltage):
Address Inputs
Data Inputs / Outputs
Power Fail Reset Output (Open Drain)
Interrupt / Frequency Test Output
(Open Drain)
Watchdog Input
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
Not connected Internally
3.3V-5V 256 Kbit (32Kb x8) TIMEKEEPER SRAM
V
V
PFD
PFD
4.5V
3.0V
Figure 1. Logic Diagram
A0-A14
WDI
W
G
E
15
44
SNAPHAT (SH)
SOH44 (MH)
V CC
V SS
M48T37Y
M48T37V
Battery
1
M48T37Y
M48T37V
8
DQ0-DQ7
RST
IRQ/FT
AI02172
1/20

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M48T37 Summary of contents

Page 1

... FREQUENCY TEST OUTPUT for REAL TIME CLOCK SOFTWARE CALIBRATION YEAR 2000 COMPLIANT AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WATCHDOG TIMER WRITE PROTECT VOLTAGE (V = Power-Fail Deselect Voltage): PFD – M48T37Y: 4.2V V 4.5V PFD – M48T37V: 2.7V V 3.0V PFD PACKAGING INCLUDES a 44-LEAD SOIC and SNAPHAT TOP (to be Ordered Separately) ...

Page 2

... DQ4 tal top in conductive foam, as this will drain the lith- ium button-cell battery. DQ3 NC As Figure 3 shows, the static memory array and the quartz controlled clock oscillator of the M48T37Y/37V are integrated on one silicon chip. Value Unit – – – ...

Page 3

... High High High Z WDI BiPORT SRAM ARRAY POWER 32,752 x 8 SRAM ARRAY V PFD RST V SS M48T37Y, M48T37V Power Standby Active IN Active OUT Active CMOS Standby Battery Back-up Mode A0-A14 DQ0-DQ7 AI03253 3/20 ...

Page 4

... C L includes JIG capacitance Note: Excluding open-drain output pins. READ MODE The M48T37Y/37V is in the Read Mode whenever Write Enable (W) is high and Chip Enable (E) is low. The unique address specified by the 15 Ad- dress Inputs defines which one of the 32,752 bytes of data accessed ...

Page 5

... OUT CC Outputs open – 0. –0.3 0 2.1mA 0 10mA 0 –1mA 2.4 OH M48T37Y, M48T37V Min Max Unit M48T37V V = 3.0V to 3.6V Unit CC Min Max –0.3 0 0.4 V 0.4 V 2.4 V ...

Page 6

... M48T37Y, M48T37V Table 7. Power Down/Up Trip Points DC Characteristics ( – Symbol Parameter V Power-fail Deselect Voltage PFD V Battery Back-up Switchover Voltage SO t Expected Data Retention Time ( Note: 1. All voltages referenced Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device). ...

Page 7

... Note 100pF 5pF tAVAV VALID tAVQV tELQV tELQX tGLQV tGLQX VALID M48T37Y V = 4.5V to 5.5V CC -70 Min Max M48T37Y, M48T37V tAXQX tEHQZ tGHQZ AI00925 M48T37V V = 3.0V to 3.6V CC Unit -10 Min Max 100 ns 100 ns 100 ...

Page 8

... V CC switches power to the internal battery which pre- serves data and powers the clock. The internal button cell will maintain data in the M48T37Y/37V for an accumulated period of at least 7 years at room temperature when V system power returns and V the battery is disconnected, and the power supply ...

Page 9

... AVWH t Address Valid to Chip Enable High AVEH (1, 2) Write Enable High to Output Transition t WHQX Note 5pF goes low simultaneously with W going low, the outputs remain in the high impedance state. M48T37Y, M48T37V M48T37Y M48T37V V = 4. 3. -70 -10 Min ...

Page 10

... CC PROGRAMMABLE INTERRUPTS The M48T37Y/37V provides two programmable interrupts; an alarm and a watchdog. When an in- terrupt condition occurs, the M48T37Y/37V sets the appropriate flag bit in the flag register 7FF0h. The interrupt enable bits in (AFE and ABE) in 10/20 tAVAV VALID ...

Page 11

... ER counters and allows normal operation to re- sume. After the WRITE bit is reset, the next clock update will occur in approximately one second. Note: Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset to ’0’. M48T37Y, M48T37V Functio n/Range BCD Format D0 Year 00-99 ...

Page 12

... Note not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT) or the STOP bit (ST). Calibrating the Clock The M48T37Y/37V is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error which equates to about 1 ...

Page 13

... AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T37Y/37V was in the deselect mode during power-up. Figure 12 illustrates the back-up mode alarm timing. 13/20 ...

Page 14

... Note: Accuracy of timer is within resolution. 14/20 If the processor does not reset the timer within the specified period, the M48T37Y/37V sets the Watchdog Flag (WDF) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 1FF0h). The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to a ‘ ...

Page 15

... V CC 0.1 F DEVICE V SS BATTERY LOW FLAG The M48T37Y/37V automatically performs period- ic battery voltage monitoring upon power-up. The Battery Low Flag (BL), Bit D4 of Flags Register 7FF0h, will be asserted high if the SNAPHAT bat- tery is found to be less than approximately 2.5V. The BL flag will remain active until completion of ...

Page 16

... M48T37Y, M48T37V Table 14. Ordering Information Scheme Example: Device Type M48T Supply Voltage and Write Protect Voltage 37Y = V = 4.5V to 5.5V 4.2V to 4.5V CC PFD 37V = V = 3.0V to 3.6V 2.7V to 3.0V CC PFD Speed -70 = 70ns -10 = 100ns Package ( SOH44 Temperature Range – Shipping Method for SOIC blank = Tubes TR = Tape & ...

Page 17

... Drawing is not to scale. mm Min Max Typ 3.05 0.05 0.36 2.34 2.69 0.36 0.46 0.15 0.32 18.49 8.23 8.89 – – 0.032 3.20 3.61 12.70 0. M48T37Y, M48T37V inches Min Max 0.120 0.002 0.014 0.092 0.106 0.014 0.018 0.006 0.012 0.697 0.728 0.324 0.350 – – 0.126 0.142 0.453 0.500 0.016 0.050 0.004 C L 17/20 ...

Page 18

... M48T37Y, M48T37V Table 17. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data Symb Typ 21.21 E 14.22 eA 15. Figure 15. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline eA D Drawing is not to scale. 18/20 mm Min Max Typ 9.78 6.73 7.24 6.48 6.99 0.38 0.46 0.56 21.84 14.99 15.95 3.20 3.61 2.03 2. inches ...

Page 19

... Figure 16. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline eA D Drawing is not to scale. mm Min Max Typ 10.54 8.00 8.51 7.24 8.00 0.38 0.46 0.56 21.84 18.03 15.95 3.20 3.61 2.03 2. M48T37Y, M48T37V inches Min Max 0.415 0.315 .0335 0.285 0.315 0.015 0.018 0.022 0.835 0.860 0.680 .0710 0.612 0.628 0.126 0.142 0.080 0.090 SHTK-A ...

Page 20

... M48T37Y, M48T37V Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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