M48T37 ST Microelectronics, M48T37 Datasheet - Page 4

• Manufacturer Part Number: M48T37
• Description: 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
• Manufacturer: ST Microelectronics

M48T37Y, M48T37V
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
The memory locations, to provide user accessible
BYTEWIDE
with addresses 7FF1 and 7FF9h-7FFFh (located
in Table 11). The clock locations contain the cen-
tury, year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year-compliant until the year 2100), 30,
and 31 day months are made automatically.
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control mi-
croprocessor and provides a reset or interrupt to it.
Byte 7FF2h-7FF5h are reserved for clock alarm
programming.
These bytes can be used to set the alarm. This will
generate an active low signal on the IRQ/FT pin
when the alarm bytes match the date, hours, min-
utes and seconds of the clock. The eight clock
bytes are not the actual clock counters them-
selves; they are memory locations consisting of Bi-
PORT
37V includes a clock control circuit which updates
the clock bytes with current information once per
second. The information can be accessed by the
user in the same manner as any other location in
the static memory array.
The M48T37Y/37V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single V
condition. When V
writes protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
below the Battery Back-up Switchover Voltage
(V
which maintains data and clock operation until val-
id power returns.
4/20
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
SO
), the control circuitry connects the battery
read/write memory cells. The M48T37Y/
clock information are in the bytes
CC
CC
supply for an out of tolerance
is out of tolerance, the circuit
CC
. As V
0 to 3V
1.5V
5ns
CC
falls
Figure 4. AC Testing Load Circuit
Note: Excluding open-drain output pins.
READ MODE
The M48T37Y/37V is in the Read Mode whenever
Write Enable (W) is high and Chip Enable (E) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,752 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (t
stable, providing that the E and Output Enable (G)
access times are also satisfied. If the E and G ac-
cess times are not met, valid data will be available
after the latter of the Chip Enable Access time
(t
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
indeterminate state until t
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
put Data Hold time (t
nate until the next Address Access.
ELQV
C L includes JIG capacitance
DEVICE
UNDER
) or Output Enable Access time (t
AVQV
TEST
AVQV
) after the last address input signal is
, the data lines will be driven to an
AXQX
C L = 100pF
AVQV
645
) but will be indetermi-
.
GLQV
AI02325
1.75V
).