SL34118N SLS [System Logic Semiconductor], SL34118N Datasheet - Page 3

• Manufacturer Part Number: SL34118N
• Description: Voice Switched Speakerphone Circuit
• Manufacturer: SLS [System Logic Semiconductor]

recommended input signal is independent of the
volume control setting. The diode clamp on the
inputs limits the input swing, and therefore the
maximum negative output swing. This is the reason
for V
they are in the Electrical Characteristics. The output
impedance is <10
(typically 2.5 mA) is reached.
output of the Control Block, which is measurable at
the C
+240 millivolts with respect to V
receive mode (receive attenuator is at +6.0 dB). When
back-to-back diodes in the feedback path, resulting in
non-linear gain, which permits operation over a wide
dynamic range of speech levels. The sensitivity of
each level detector is determined by the external
resistor and capacitor at each input (TLI1, TLI2, RLI1,
and RLI2). Each output charges an external capacitor
through a diode and limiting resistor, thus providing a
dc
SLS
The attenuators are controlled by the single
Each level detector is a high gain amplifier with
RXOL
representation
T
pin (Pin 14). When the C
System Logic
Semiconductor
Figure 1. Attenuator Input Stage
and V
TXOL
specification being defined as
until the output current limit
of
the
B
, the circuit is in the
input
T
ac
pin is at
Figure 2. Level Detectors
signal
the C
circuit is in the transmit mode (transmit attenuator is
at +6.0 dB). The circuit is in an idle mode when the C
voltage is equal to V
to be halfway between their fully on and fully off
positions ( - 20 dB each). Monitoring the C
(with respect to V
monitoring the circuit’s mode.
the comp arators operated by the level detectors, 2
from the background noise monitors, the volume
control, the dial-tone detector, and the AGC circuit.
These seven inputs are described below.
LEVEL DETECTORS
side and two on the transmit side. Refer to Figure
2 - the terms in parentheses form one system, and the
other
level. The outputs have a guick rise time (determined
by the capacitor and an internal 350
slow decay time set by an internal current source and
the capacitor. The capacitors on the four outputs
should have the same value ( 10%) to prevent timing
problems.
level detector (RLI1) is at the receive input receiving
the same signal as at Tip and Ring, and
The inputs to the Control Block are seven: 2 from
There are four level detectors - two on the receive
Referring to Figure 8, on the receive side, one
T
pin is at -240 millivolts with respect to V
terms
form
B
B
) is the most direct method of
, causing the attenuators’ gains
the
second
SL34118
resistor), and a
T
voltage
system
B
, the
T