ISL59911IRZ INTERSIL [Intersil Corporation], ISL59911IRZ Datasheet - Page 13

• Manufacturer Part Number: ISL59911IRZ
• Description: 250MHz Triple Differential Receiver/ Equalizer with I2C Interface
• Manufacturer: INTERSIL [Intersil Corporation]

ISL59911 Serial Communication
Overview
The ISL59911 uses the I
communication with its host (master). SCL is the Serial Clock
line, driven by the host, and SDA is the Serial Data line, which can
be driven by all devices on the bus. SDA is open drain to allow
multiple devices to share the same bus simultaneously.
Communication is accomplished in three steps:
The ISL59911 has a 7-bit address on the serial bus,
10001<a1><a0>b, where 10001 is fixed and a0 and a1 are the
state of the ADDR0 and ADDR1 pins, respectively. This allows up
to four ISL59911 devices to be independently controlled by the
same serial bus.
To control more than four devices (or more than two, if ADDR1 is
tied low as discussed in “Power Supply Sequencing” on page 10)
from a single I
For example, in the firmware, the host can fix the I
1000101b for all devices, selecting the device to be
communicated to by taking its ADDR0 pin high while the ADDR0
pins of all other devices remain low. The selected device
1. The host selects the ISL59911 it wishes to communicate
2. The host writes the initial ISL59911 Configuration Register
3. The host writes to or reads from the ISL59911s Configuration
with.
address it wishes to write to or read from.
Register. The ISL59911s internal address pointer auto
increments, so to read registers 0x00 through 0x1B, for
example, one would write 0x00 in step 2, then repeat step
three 28 times, with each read returning the next register
value.
2
FROM TRANSMITTER
C host, use a “chip select” signal for each device.
FROM RECEIVER
DATA OUTPUT
DATA OUTPUT
SCL FROM
2
C serial bus protocol for
SDA
SCL
HOST
13
START
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 14. VALID START AND STOP CONDITIONS
2
C address to
START
1
ISL59911
recognizes its current address (1000101b) and respond
normally, while the remaining devices will have an address of
1000100b and therefore ignore the communication. This
requires one additional GPIO for each ISL59911, but it permits
as many ISL59111 devices to be controlled as desired, without
any additional external logic.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START command
by taking SDA low while SCL is high (Figure 14). The ISL59911
continuously monitors the SDA and SCL lines for the start
condition and does not respond to any command until this
condition has been met. The host then transmits the 7-bit serial
address plus a R/W bit, indicating if the next transaction is a
Read (R/W = 1) or a Write (R/W = 0). If the address transmitted
matches that of any device on the bus, that device must respond
with an ACKNOWLEDGE (Figure 15).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be written
to or read from the slave. Communication with the selected
device in the selected direction (read or write) is ended by a STOP
command, where SDA rises while SCL is high (Figure 14), or a
second START command, which is commonly used to reverse
data direction without relinquishing the bus.
The I
for the entire time SCL is high (Figure 16). To ensure incoming
data has settled, data written to the ISL59911 is latched on a
delayed version of the rising edge of SCL.
When the contents of the ISL59911 are being read, the SDA line
is updated after the falling edge of SCL, delayed and deglitched
in the same manner.
2
C spec requires that data on the serial bus must be valid
8
STOP
ACKNOWLEDGE
9
September 2, 2011
FN7548.0