ISL59911IRZ INTERSIL [Intersil Corporation], ISL59911IRZ Datasheet - Page 9

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ISL59911IRZ

Manufacturer Part Number
ISL59911IRZ
Description
250MHz Triple Differential Receiver/ Equalizer with I2C Interface
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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ISL59911IRZ
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Part Number:
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Register Listing
NOTE: All registers are read/write unless otherwise noted.
0x0B
0x0C
0x0D - 0x12 Reserved
0x13
ADDRESS
Blue Channel Manual Offset (0x00)
(Default is auto-calibrated)
Offset Calibration Control (0x00)
Initialization
REGISTER (DEFAULT VALUE)
9
(Continued)
BIT(S)
6:0
7:0
7:0
7
0
1
2
ISL59911
Blue Offset
Manual Offset Control
(Blue)
Start Cal
Cal Mode
Short Inputs
Reserved
Initialization
FUNCTION NAME
0x00: -400mV Offset
0x7F: +400mV Offset
(Output Referred)
0: Offset is auto calibrated - value in bits 6:0 is ignored
1: Offset DAC set to value in bits 6:0
Set to 1 to initiate offset calibration. Bit is reset to 0 when
calibration is complete (in ~3µs or less).
0: Analog inputs disconnected from external pins and
internally shorted together during calibration.
1: Analog inputs remain connected to external circuitry
during calibration. Useful for calibrating out system-wide
offsets. External offsets of up to ~±160mV can be
eliminated.
0: Normal operation
1: Inputs shorted together (independent of the Cal Mode bit)
Reserved. Do not write anything to these addresses.
After initial power on, write 0x06 to this register,
followed by a write of 0x00 to this register.
DESCRIPTION
September 2, 2011
FN7548.0

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