AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 18

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

AD14160/AD14160L
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
W = (number of wait states specified in WAIT register)
HI = t
H = t
NOTES
1
2
3
4
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the AD14160/
AD14160L is the bus master accessing external memory space.
DAD
DRLD
HDA
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
SADADC
Data Delay/Setup: User must meet t
For MSx, SW, BMS, the falling edge is referenced.
Data Hold: User must meet t
given capacitive and dc loads.
ACK Delay/Setup: User must meet t
CK
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
Address, Selects Delay to Data Valid
RD Low to Data Valid
Data Hold from Address
Data Hold from RD High
ACK Delay from Address
ACK Delay from RD Low
Address Hold After RD High
Address to RD Low
RD Pulsewidth
RD High to WR, RD, DMAGx Low
Address Setup Before ADRCLK High
ADDRESS
WR, DMAG
MSx, SW
ADRCLK
DATA
(OUT)
BMS
ACK
RD
HDA
or t
DAD
HDRH
2
DSAK
t
SADADC
1
or t
or t
or synchronous spec t
3
t
2, 4
DRLD
3
DARL
4
DAAK
t
DAAK
or synchronous spec t
or synchronous specification t
Figure 14. Memory Read—Bus Master
t
1, 2
CK.
2
t
DSAK
t
DAD
Min
1.5
3
–1 + H
1 + 3DT/8
12.5 + 5DT/8 + W
7.5 + 3DT/8 + HI
–0.5 + DT/4
HDATI
. See System Hold Time Calculation under Test Conditions for the calculation of hold times
t
DRLD
40 MHz–5 V
SSDATI
.
–18–
SACKC
t
These switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write—Bus
Master below). If these timing requirements are met, the syn-
chronous read/write timing can be ignored (and vice versa).
RW
.
Max
17 + DT + W
11 + 5DT/8 + W
13 + 7DT/8 + W
7 + DT/2 + W
Min
1.5
3
–1 + H
1 + 3DT/8
12.5 + 5DT/8 + W
7.5 + 3DT/8 + HI
–0.5 + DT/4
40 MHz–3.3 V
t
HDRH
t
t
HDA
DRHA
t
RWR
Max
17 + DT + W
11 + 5DT/8 + W
13 + 7DT/8 + W
7 + DT/2 + W
REV. A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns