AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 38

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

AD14160/AD14160L
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by V is dependent on the capacitive load, C
the load current, I
the following equation:
The output disable time, t
and t
interval from when the reference signal switches to when the
output voltage decays V from the measured output high or
output low voltage. t
I
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time, t
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 28). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
voltage and the input threshold for the device requiring the hold
time. A typical V will be 0.4 V. C
(per data line), and I
(per data line). The hold time will be t
disable time (i.e., t
L
V to be the difference between the ADSP-2106x’s output
, and with V equal to 0.5 V.
DECAY
as shown in Figure 28. The time t
DECAY
L
HDWD
. This decay time can be approximated by
DECAY
L
using the equation given above. Choose
is the total leakage or three-state current
t
DECAY
for the write cycle).
DIS
is calculated with test loads C
, is the difference between t
C
ENA
L
L
I
is the total bus capacitance
L
, is the interval from when
V
DECAY
MEASURED
plus the minimum
is the
MEASURED
L
L
and
, and
–38–
Figure 30. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 29). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 31, 32, 33
and 34 show how output rise time varies with capacitance.
Figures 35 and 36 graphically show how output delays and
holds vary with load capacitance. (Note that these graphs or
derating does not apply to output disable delays; see the previ-
ous section Output Disable Time under Test Conditions.) The
graphs of Figures 31 through 36 may not be linear outside the
ranges shown.
REFERENCE
V
V
Figure 29. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
OH (MEASURED)
OL (MEASURED)
SIGNAL
INPUT OR
OUTPUT
t
DIS
OUTPUT
OUTPUT STOPS
Figure 28. Output Enable/Disable
PIN
DRIVING
TO
50pF
1.5V
t
MEASURED
V
V
OH (MEASURED)
OL (MEASURED)
t
DECAY
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
+ V
I
– V
I
OH
OL
OUTPUT STARTS
t
ENA
1.0V
2.0V
DRIVING
+1.5V
1.5V
V
V
OH (MEASURED)
OL (MEASURED)
REV. A