PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 387

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

LFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
After Instruction
Decode
Decode
FSR2H
FSR2L
Q1
Read literal
Read literal
‘k’ MSB
Load FSR
LFSR f, k
0
0
k
None
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
2
2
‘k’ LSB
LFSR 2, 3ABh
1110
1111
Q2
=
=
f
k
FSRf
2
4095
03h
ABh
1110
0000
Process
Process
Data
Data
Q3
k
00ff
7
kkk
‘k’ to FSRfL
Write literal
literal ‘k’
MSB to
FSRfH
PIC18F2480/2580/4480/4580
Write
k
Q4
kkkk
11
kkk
Preliminary
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
W
REG
W
Q1
register ‘f’
Move f
MOVF
0
d
a
f
N, Z
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
MOVF
Read
0101
Q2
=
=
=
=
f
[0,1]
[0,1]
dest
255
22h
FFh
22h
22h
f {,d {,a}}
REG, 0, 0
00da
Process
Data
Q3
DS39637A-page 385
95 (5Fh). See
ffff
Write W
Q4
ffff