PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 409
PIC18F2480
Manufacturer Part Number
PIC18F2480
Description
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2480.pdf
(484 pages)
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SUBFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
=
=
register ‘f’
SUBFSR f, k
0
f
FSRf – k
None
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
1
1
SUBFSR 2, 23h
Subtract Literal from FSR
Read
1110
Q2
03FFh
03DCh
k
[ 0, 1, 2 ]
63
1001
FSRf
Process
Data
Q3
ffkk
destination
Write to
PIC18F2480/2580/4480/4580
kkkk
Q4
Preliminary
SUBULNK
Syntax:
Operands:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Operation
Decode
No
FSR2
PC
FSR2
PC
Q1
Subtract Literal from FSR2 and Return
SUBULNK k
0
FSR2 – k
(TOS)
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the TOS.
The instruction takes two cycles to execute;
a NOP is performed during the second cycle.
This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary
‘11’); it operates only on FSR2.
1
2
1110
=
=
=
=
k
register ‘f’
Operation
SUBULNK 23h
Read
63
No
Q2
03FFh
0100h
03DCh
(TOS)
PC
FSR2
1001
Operation
Process
Data
No
Q3
DS39637A-page 407
11kk
destination
Operation
Write to
No
kkkk
Q4
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