ADCMP606_0610 AD [Analog Devices], ADCMP606_0610 Datasheet - Page 5

• Manufacturer Part Number: ADCMP606_0610
• Description: Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
• Manufacturer: AD [Analog Devices]

TIMING INFORMATION
Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
Table 2. Timing Descriptions
Symbol
t
t
t
t
t
t
t
t
t
V
F
H
PDH
PDL
PL
PLOH
PLOL
R
S
OD
Timing
Output fall time
Minimum hold time
Input to output high delay
Input to output low delay
Minimum latch enable pulse width
Latch enable to output high delay
Latch enable to output low delay
Output rise time
Minimum setup time
Voltage overdrive
INPUT VOLTAGE
LATCH ENABLE
DIFFERENTIAL
Q OUTPUT
Q OUTPUT
V
IN
Description
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
Minimum time that the latch enable signal must be high to acquire an input signal change.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
Difference between the input voltages V
Figure 2. System Timing Diagram
V
t
S
OD
t
t
PDL
PDH
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t
H
t
R
t
F
t
PL
t
t
PLOH
PLOL
A
and V
B
.
ADCMP606/ADCMP607
1.1V
V
50%
50%
N
± V
OS