93LC46-ISL MICROCHIP [Microchip Technology], 93LC46-ISL Datasheet - Page 3

• Manufacturer Part Number: 93LC46-ISL
• Description: 1K/2K/4K 2.0V Microwire Serial EEPROM
• Manufacturer: MICROCHIP [Microchip Technology]

2.0
2.1
A high level selects the device. A low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93LCXX.
Opcodes, addresses, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing the opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1 to Table 2-6). CLK and DI then become don't
care inputs waiting for a new START condition to be
detected.
1997 Microchip Technology Inc.
Note:
PIN DESCRIPTION
Chip Select (CS)
Serial Clock (CLK)
CS must go low between consecutive
instructions.
CKL
). This gives the controlling master
CSL
) between
CKH
) and
2.3
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4
Data Out (DO) is used in the READ mode to output data
synchronously with the CLK input (T
tive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
been initiated.
The status signal is not available on DO, if CS is held
low or high during the entire WRITE or ERASE cycle. In
all other cases DO is in the HIGH-Z mode. If status is
checked after the ERASE/WRITE cycle, a pull-up
resistor on DO is required to read the READY signal.
2.5
When ORG is tied to V
tion is selected. When ORG is connected to Vcc or
floated, the (x16) memory organization is selected.
ORG can only be floated for clock speeds of 1 MHz or
less for the (X16) memory organization. For clock
speeds greater than 1 MHz, ORG must be tied to Vcc
or V
SS
.
Data In (DI)
Data Out (DO)
Organization (ORG)
CSL
) and an ERASE or WRITE operation has
93LC46/56/66
SS
, the (x8) memory organiza-
PD
DS11168L-page 3
after the posi-