93LC46-ISL MICROCHIP [Microchip Technology], 93LC46-ISL Datasheet - Page 8

• Manufacturer Part Number: 93LC46-ISL
• Description: 1K/2K/4K 2.0V Microwire Serial EEPROM
• Manufacturer: MICROCHIP [Microchip Technology]

93LC46/56/66
3.8
The WRITE instruction is followed by 8 bits (or by 16
bits) of data which are written into the specified
address. After the last data bit is put on the DI pin, CS
must be brought low before the next rising edge of the
CLK clock. This falling edge of CS initiates the self-
timed auto-erase and programming cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion.
The WRITE cycle takes 4 ms per word (Typical).
FIGURE 3-7:
FIGURE 3-8:
DS11168L-page 8
CLK
CLK
CS
CS
Guarantee at Vcc = +4.5V to +6.0V.
DO
DO
DI
DI
CSL
WRITE
) and before the entire write cycle is complete.
WRITE TIMING
WRAL TIMING
1
1
TRI-STATE
TRI-STATE
0
0
0
1
•A
0
n
• • •
1
X
A0
• • •
Dx
X
• • •
3.9
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the self clocking mode. The WRAL command does
include an automatic ERAL cycle for the device. There-
fore, the WRAL instruction does not require an ERAL
instruction, but the chip must be in the EWEN status.
The WRAL instruction is guaranteed at V
+6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
The WRAL cycle takes 30 ms maximum (16 ms typical).
Dx
D0
CSL
• • •
T
CSL
Write All (WRAL)
).
D0
T
WC
BUSY
T
CSL
T
WL
BUSY
1997 Microchip Technology Inc.
READY
READY
CC
STANDBY
TRI_STATE
STANDBY
TRI-STATE
= +4.5V to