M95320-W STMICROELECTRONICS [STMicroelectronics], M95320-W Datasheet - Page 24

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M95320-W

Manufacturer Part Number
M95320-W
Description
32 Kbit and 64 Kbit Serial SPI bus EEPROMs with high speed clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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Power-up and delivery state
7
7.1
7.2
24/44
Power-up and delivery state
Power-up state
After Power-up, the device is in the following state:
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
Standby Power mode
deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
not in the Hold Condition
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
M95320, M95640, M95320-x, M95640-x

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