R2J20602NP-G3 RENESAS [Renesas Technology Corp], R2J20602NP-G3 Datasheet - Page 12

• Manufacturer Part Number: R2J20602NP-G3
• Description: Integrated Driver - MOS FET (DrMOS)
• Manufacturer: RENESAS [Renesas Technology Corp]

R2J20602NP
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET,
low-side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.
Driver
The driver has two types of power-supply voltage input pin, VCIN and VLDRV. VCIN supplies the operating voltage
to the internal logic circuit. The low-side driving voltage is applied to VLDRV, so setting of the gate-driving voltage for
the low-side MOS FET is independent of the voltage on VCIN. The VLDRV setting voltage is from 5 V to 16 V.
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN
is 7.4 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 7.0 V or less. The
signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit, the built-in 5 V regulator
does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and
the 5 V regulator is not disabled.
Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor,
etc., to pull the DISBL# line up to VCIN are both possible.
The built-in 5 V regulator is a series regulator with temperature compensation. The voltage output by this regulator
determines the operating voltage of the internal logic and gate-voltage swing for the high-side MOS FET. A ceramic
capacitor with a value of 0.1 F or more must be connected between the CGND plane and the Reg5V pin.
The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (Reg5V + 3 V). When
the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is
low.
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 10 of 14
PWM
VCIN
H
H
H
H
L
L
VLDRV
> 5 V
> 5 V
> 5 V
> 5 V
GH
H
L
DISBL#
Open
GL
H
H
L
L

Reg5V
5 V
5 V
5 V
0
Disable (GL, GH = L)
Disable (GL, GH = L)
Active
Disable (GL, GH = L)
Driver State