FDMF3030 FAIRCHILD [Fairchild Semiconductor], FDMF3030 Datasheet - Page 13

• Manufacturer Part Number: FDMF3030
• Description: Extra-Small, High-Performance, High-Frequency, DrMOS Module
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2012 Fairchild Semiconductor Corporation
FDMF3030 • Rev. 1.0.0
Adaptive Gate Drive Circuit
The driver IC advanced design ensures minimum
MOSFET dead-time, while eliminating potential shoot-
through (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 29
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
VSWH
VSWH
PWM
GH
GL
to
Notes:
t
t
PWM
t
t
t
ZCD_EN#
t
t
PD_xxx
D_xxx
PD_PHGLL
PD_PLGHL
PD_PHGHH
PD_ZLGLL
PD_ZHGLH
V
IH_PWM
= delay from IC generated signal to IC generated signal.
= propagation delay from external signal (PWM, ZCD_EN#, etc.) to IC generated signal.
= ZCD_EN# fall to LS V
= PWM rise to LS V
= PWM fall to HS V
= ZCD_EN# rise to LS V
= PWM rise to HS V
t
CCM
PD_PHGLL
t
D_DEADON
1.7V
90%
t
PD_PLGHL
GS
GS
GS
fall, V
fall, V
GS
rise, V
GS
fall, V
V
rise, V
t
IL PWM
D_DEADOFF
IH_PWM
IL_PWM
IH_PWM
IL_ZCD_EN
t
1.7V
R_GL
IH_ZCD_EN
to 90% HS V
to 90% LS V
to 10% HS V
10%
t
to 90% LS V
less than
D_HOLD‐OFF
to 10% LS V
Figure 29.
GS
GS
GS
GS
t
(ZCD_EN# held LOW)
D_HOLD‐OFF
GS
3 ‐State
Enter
Example (t
t
F_GL
DCM
V
PWM and 3-StateTiming Diagram
D_DEADON
IH_PWM
3‐State
Exit
t
– LS Vgs (GL) LOW to HS Vgs (GH) HIGH)
t
R_GH
PD_TSGHH
13
Exiting 3‐state
t
t
Dead Times
t
t
PD_TSGHH
PD_TSGLH
D_DEADON
D_DEADOFF
HIGH, Q2 begins to turn off after a propagation delay
(t
Q1 begins to turn on after adaptive delay t
To prevent overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the GH-to-PHASE pin pair. When the PWM
signal goes LOW, Q1 begins to turn off after a
propagation delay (t
GH-to-PHASE falls below 1.7V, Q2 begins to turn on
after adaptive delay t
t
PD_PHGLL
D_HOLD‐OFF
Example (t
V
TRI_HI
= PWM 3‐state to LOW to LS V
= PWM 3‐state to HIGH to HS V
= LS V
= VSWH fall to LS V
3 ‐State
Enter
t
F_GH
GS
PD_PHGLL
fall to HS V
). Once the GL pin is discharged below 1.7V,
DCM
– PWM going HIGH to LS Vgs (GL) going LOW)
V
IH_PWM
GS
GS
rise, LS‐comp trip value (~1.7V GL) to 10% HS V
rise, SW‐comp trip value (~1.7V VSWH) to 10% LS V
t
3‐ State
PD_TSGHH
Exit
PD_PLGHL
D_DEADOFF
GS
GS
rise, V
rise, V
t
less than
D_HOLD‐OFF
IL_PWM
). Once the voltage across
IH_PWM
.
to 10% LS V
to 10% HS V
t
3 ‐State
D_HOLD‐OFF
Enter
GS
GS
D_DEADON
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t
3‐State
PD_TSGLH
Exit
GS
V
V
V
V
GS
IH_PWM
TRI_LO
TRI_HI
IL_PWM
.
V
V
90%
10%
90%
10%
OUT
IN