FDMF3030 FAIRCHILD [Fairchild Semiconductor], FDMF3030 Datasheet - Page 14

• Manufacturer Part Number: FDMF3030
• Description: Extra-Small, High-Performance, High-Frequency, DrMOS Module
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2012 Fairchild Semiconductor Corporation
FDMF3030 • Rev. 1.0.0
Zero Cross Detection Mode (ZCD_EN#)
The Zero Cross Detection Mode allows for higher
converter
conditions. When ZCD_EN# is pulled LOW; the low-side
MOSFET gate signal pulls LOW when internal circuitry
detects positive LS MOSFET drain current, preventing
discharge of the output capacitors as the filter inductor
current attempts reverse current flow – known as “Diode
Emulation” Mode.
When
synchronous buck converter works in Synchronous
Mode, which allows for gating of the low-side MOSFET.
Table 2.
Note:
4.
ZCD_EN#
VSWH
GH to
PWM
VSWH
GL
V
GL = 0, when I
current is positive and flowing out of the DrMOS VSWH node).
IH_PWM
DISB#
the
t
PD_PHGLL
0
1
1
1
1
1
efficiency
t
ZCD_EN# Logic
D_DEADON
ZCD_EN#
1.7V
90%
L
< 0 (Inductor current is negative and flowing in to the DrMOS VSWH node). GL = 1 when I
t
PD_PLGHL
t
D_DEADOFF
when
V
90%
IL_PWM
1.7V
pin
3-State
PWM
10%
operating
X
is
0
1
0
1
pulled
I
L
Figure 30.
> 0
GL transitions
detected and
I
V
L
in
low.
< 0
IL_ZCD_EN
HIGH,
light-load
ZCD_EN#
ZCD_EN# Timing Diagram
the
going high to LS V
X
X
0
0
1
1
Delay from ZCD_EN#
V
IH_ZCD_EN
14
DCM (I
When the ZCD_EN# pin is pulled LOW, the low-side
MOSFET is gated off automatically during positive LS
MOSFET drain current. If the ZCD_EN# pin is pulled
LOW by the PWM controller to support light-load Power-
Saving Mode, FDMF3030 can actively turn off the low-
side MOSFET when it detects the zero crossing of the
inductor current. The low-side MOSFET turns on when
inductor current is positive (LS MOSFET drain current is
negative) and turns off when inductor current is negative
(LS MOSFET drain current is positive). Zero-crossing
detection of the inductor current and low-side MOSFET
on and off are automatically performed on a cycle-by-
cycle basis. Normally this pin is active LOW. See Figure
30 for timing delays.
t
PD_ZHGLH
GS
L
= 0)
high
10%
t
PD_ZLGLL
going low to LS V
Delay from ZCD_EN#
GH
V
0
0
0
1
0
1
IL_ZCD_EN
90%
V
GS
DCM
IH_PWM
low
t
PD_PHGLL
0 (I
1 0%
L
L
> 0 (Inductor
<0),1 (I
GL
www.fairchildsemi.com
0
0
0
1
0
V
OUT
L
> 0)
(4)