FDMF3030 FAIRCHILD [Fairchild Semiconductor], FDMF3030 Datasheet - Page 16

• Manufacturer Part Number: FDMF3030
• Description: Extra-Small, High-Performance, High-Frequency, DrMOS Module
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2012 Fairchild Semiconductor Corporation
FDMF3030 • Rev. 1.0.0
PCB Layout Guidelines
Figure 32 and Figure 33 provide an example of a proper
layout for the FDMF3030 and critical components. All of
the high-current paths; such as VIN, VSWH, VOUT, and
GND copper; should be short and wide for low
inductance and resistance. This aids in achieving a
more stable and evenly distributed current flow, along
with enhanced heat radiation and system performance.
Recommendations for PCB Designers
Input ceramic bypass capacitors must be placed close
to the VIN and PGND pins. This reduces the high-
current power loop inductance and the input current
ripple induced by power MOSFET switching operation.
The V
to being the high-frequency current path from the
DrMOS package to the output inductor, it serves as a
heat sink for the low-side MOSFET in the DrMOS
package. The trace should be short and wide enough to
present a low-impedance path for the high-frequency,
high-current flow between the DrMOS and inductor. The
short and wide trace minimizes electrical losses as well
as the DrMOS temperature rise. The V
high-voltage and high-frequency switching node with
high noise potential. Care should be taken to minimize
coupling to adjacent traces. Since this copper trace acts
as a heat sink for the lower MOSFET, balance using the
largest area possible to improve DrMOS cooling while
maintaining acceptable noise emission.
An output inductor should be located close to the
FDMF3030 to minimize the power loss due to the V
copper trace. Care should also be taken so the inductor
dissipation does not heat the DrMOS.
PowerTrench
and minimize ringing due to fast switching. In most
cases, no VSWH snubber is required. If a snubber is
used, it should be placed close to the VSWH and PGND
pins. The selected resistor and capacitor need to be the
proper size for power dissipation.
VCIN, VDRV, and BOOT capacitors should be placed
as close as possible to the VCIN-to-CGND, VDRV-to-
CGND, and BOOT-to-PHASE pin pairs to ensure clean
and stable power. Routing width and length should be
considered as well.
Include a trace from the PHASE pin to the VSWH pin to
improve noise margin. Keep this trace as short as possible.
The layout should include the option to insert a small-
value series boot resistor between the boot capacitor
and BOOT pin. The boot-loop size, including R
C
BOOT
, should be as small as possible. The boot resistor
SWH
copper trace serves two purposes. In addition
®
MOSFETs are used in the output stage
SWH
node is a
BOOT
and
SWH
16
may be required when operating above 15V
effective at controlling the high-side MOSFET turn-on
slew rate and V
operating margin in synchronous buck designs that may
have noise issues due to ground bounce or high positive
and negative V
lowers the DrMOS efficiency. Efficiency versus noise
trade-offs must be considered. R
to 3.0 are typically effective in reducing V
The VIN and PGND pins handle large current transients
with frequency components greater than 100MHz. If
possible, these pins should be connected directly to the
VIN and board GND planes. The use of thermal relief
traces in series with these pins is discouraged since this
adds inductance to the power path. This added
inductance in series with either the VIN or PGND pin
degrades system noise immunity by increasing positive
and negative V
GND pad and PGND pins should be connected to the
GND copper plane with multiple vias for stable
grounding. Poor grounding can create a noise transient
offset voltage level between CGND and PGND. This
could lead to faulty operation of the gate driver and
MOSFETs and should be avoided.
Ringing at the BOOT pin is most effectively controlled
by close placement of the boot capacitor. Do not add an
additional BOOT to the PGND capacitor. This may lead
to excess current flow through the BOOT diode.
The ZCD_EN# and DISB# pins have weak internal pull-
up and pull-down current sources, respectively. These
pins should not have any noise filter capacitors. Do not
to float these pins unless absolutely necessary.
Use multiple vias on the VIN and VOUT copper areas to
interconnect top, inner, and bottom layers to distribute
current flow and heat conduction. Do not put many vias
on the VSWH copper to avoid extra parasitic inductance
and noise on the switching waveform. As long as
efficiency and thermal performance are acceptable,
place only one VSWH copper on the top layer and use
no vias on the VSWH copper to minimize switch node
parasitic noise. Vias should be relatively large and of
reasonably low inductance. Critical high-frequency
components, such as R
bypass capacitors; should be located as close to the
respective DrMOS module pins as possible on the top
layer of the PCB. If this is not feasible, they can be
connected from the backside through a network of low-
inductance vias.
SWH
SHW
SWH
ringing.
overshoot. R
ringing. Inserting a boot resistance
BOOT
, C
BOOT
BOOT
BOOT
, RC snubber, and
can improve noise
values from 0.5
SWH
www.fairchildsemi.com
overshoot.
IN
and is