ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 155

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

USART Baud Rate Registers –
UBRRL and UBRRHs
2486M–AVR–12/03
This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous
mode is used. The UCPOL bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCK).
Table 59. UCPOL Bit Settings
The UBRRH Register shares the same I/O location as the UCSRC Register. See the
“Accessing UBRRH/UCSRC Registers” on page 149 section which describes how to
access this register.
• Bit 15 – URSEL: Register Select
This bit selects between accessing the UBRRH or the UCSRC Register. It is read as
zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.
• Bit 14:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit
must be written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the
four most significant bits, and the UBRRL contains the eight least significant bits of the
USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor-
rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of
the baud rate prescaler.
Bit
Read/Write
Initial Value
UCPOL
0
1
Transmitted Data Changed (Output of
TxD Pin)
Rising XCK Edge
Falling XCK Edge
URSEL
R/W
R/W
15
7
0
0
R/W
14
R
–
6
0
0
R/W
13
R
–
5
0
0
R/W
12
R
–
4
0
0
UBRR[7:0]
R/W
R/W
11
3
0
0
Received Data Sampled (Input on
RxD Pin)
Falling XCK Edge
Rising XCK Edge
R/W
R/W
10
2
0
0
UBRR[11:8]
ATmega8(L)
R/W
R/W
9
1
0
0
R/W
R/W
8
0
0
0
UBRRH
UBRRL
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