ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 170

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

TWI Status Register – TWSR
TWI Data Register – TWDR
TWI (Slave) Address Register
– TWAR
170
ATmega8(L)
• Bits 7..3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The differ-
ent status codes are described later in this section. Note that the value read from TWSR
contains both the 5-bit status value and the 2-bit prescaler value. The application
designer should mask the prescaler bits to zero when checking the Status bits. This
makes status checking independent of prescaler setting. This approach is used in this
datasheet, unless otherwise noted.
• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 65. TWI Bit Rate Prescaler
To calculate bit rates, see “Bit Rate Generator Unit” on page 167. The value of
TWPS1..0 is used in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the
TWDR contains the last byte received. It is writable while the TWI is not in the process of
shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.
Note that the Data Register cannot be initialized by the user before the first interrupt
occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted
out, data on the bus is simultaneously shifted in. TWDR always contains the last byte
present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In
this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no
data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled
automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte
received on the Two-wire Serial Bus.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
TWPS1
0
0
1
1
TWS7
TWD7
R/W
R
7
1
7
1
7
TWS6
TWD6
R/W
R
6
1
TWPS0
0
1
0
1
6
1
6
TWS5
TWD5
R/W
R
5
1
5
1
5
TWS4
TWD4
R/W
R
4
1
4
1
4
TWS3
Prescaler Value
1
4
16
64
TWD3
R/W
R
3
1
3
1
3
TWD2
R/W
R
2
–
0
2
1
2
TWPS1
TWD1
R/W
R/W
1
0
1
1
1
TWPS0
TWD0
R/W
R/W
0
0
0
1
0
2486M–AVR–12/03
TWSR
TWDR