MC908GR16ACFA FREESCALE [Freescale Semiconductor, Inc], MC908GR16ACFA Datasheet - Page 176

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MC908GR16ACFA

Manufacturer Part Number
MC908GR16ACFA
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
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System Integration Module (SIM)
15.3 Reset and System Initialization
The MCU has these reset sources:
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see
the resets sets a corresponding bit in the SIM reset status register (SRSR). See
15.3.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset.
See
15.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset continues to be asserted for an additional 32 cycles at which point
the reset vector will be fetched. See
illegal opcode, COP timeout, LVI, or POR. See
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
176
Table 15-2
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
Forced monitor mode entry reset (MODRST)
CGMOUT
RST
IAB
For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in
for details.
PC
Figure 15-4
Figure 15-4. External Reset Timing
MC68HC908GR16A Data Sheet, Rev. 1.0
Figure
shows the relative timing.
15-5. An internal reset can be caused by an illegal address,
15.4 SIM
Figure
NOTE
15-6.
Counter), but an external reset does not. Each of
VECT H
VECT L
Figure
15.7 SIM Registers.
15-5.
Freescale Semiconductor

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